Semiconductor Wafer Metallization Channels for Solder Void Reduction

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Solution Overview

Problem

Current die solder attach processes in semiconductor wafer fabrication often result in voids and gas bubbles in the solder joint, affecting thermal and electrical performance and leading to potential overheating and device damage, with existing solutions limited to patterning substrates and requiring a 'stack-up' structure.

Innovation Solution

A method involving the formation of channels in the metallisation layer on the semiconductor wafer, allowing gases to escape during the soldering process, thereby reducing void formation without the need for patterning substrates or multiple layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional solder attach processes are used, then die attachment is achieved, but voids and gas bubbles form in the solder joint affecting thermal and electrical performance

Engineering Contradiction:
Improvesolder joint qualityVSAvoidvoid formation
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The metallisation layer is designed with an array of channels forming a porous structure that allows gas to escape during soldering. The channels are distributed across the metallisation layer in a pattern that facilitates gas venting while maintaining electrical and thermal conductivity. This porous structure enables the solder joint to form without trapped gases, eliminating voids and improving reliability.

Inventive Principle:
Principle #31Porous materials

Solution Approach 2:

The metallisation layer is segmented into multiple regions by the channel array, creating distinct pathways for gas escape. The channels divide the continuous metallisation layer into separated conductive regions that remain electrically connected through the channel structure, allowing gas to vent while maintaining electrical functionality.

Inventive Principle:
Principle #1Segmentation

2Reliability

If channels are formed in the metallisation layer, then gas escape paths are created reducing voids, but the metallisation layer structure becomes more complex

Engineering Contradiction:
Improvevoid reductionVSAvoidmetallisation layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The metallisation layer incorporates a porous channel structure that provides gas escape pathways. The channels are formed as integrated features within the metallisation layer itself, creating a porous material that maintains conductivity while enabling gas venting. This approach adds structural complexity only to the extent necessary for gas escape, without requiring additional separate components.

Inventive Principle:
Principle #31Porous materials

3Reliability

If channels are formed in the metallisation layer, then gas escape is enabled, but manufacturing process complexity increases

Engineering Contradiction:
Improvegas venting capabilityVSAvoidmetallisation layer fabrication
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The channels are formed in the metallisation layer during the wafer fabrication process before the die are separated and attached to the substrate. This preliminary formation of channels integrates the gas escape structure into the standard manufacturing flow, avoiding the need for additional post-processing steps and reducing overall manufacturing complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The channel formation is merged with the metallisation layer deposition process, combining two functions (creating conductive pathways and gas escape routes) into a single integrated structure. This merging of functions during fabrication simplifies the manufacturing process by eliminating separate steps for channel creation.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8456023B2Semiconductor wafer processing
Publication Date: 2013.06.04 NXP USA INC
  • US8456023B2 patent drawing
  • US8456023B2 patent drawing
  • US8456023B2 patent drawing

AI summary

A method of processing a semiconductor wafer is provided which comprises treating a metallization layer provided on a backside of the wafer to form a plurality of channels therein, such that at least some of the channels along substantially the length thereof extend through the thickness of the metallization layer to the backside of the wafer, thereby exposing the material of the backside of the wafer. When the semiconductor wafer is separated into dies, each die is provided with a plurality of channels, which extend to an edge of the die. On attaching the die to a die attach flag by solder, the solder does not stick to the exposed material of the backside of the die, and channels are thereby formed in the solder. This allows venting of gases formed in the solder, and decreases void formation in the solder.