Wafer Metrology Sub-Sampling with Smart Interpolation
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Solution Overview
Problem
Conventional metrology processes for semiconductor wafer fabrication are inefficient due to the need for extensive measurements at fixed locations, which limits the accuracy of process monitoring and control, especially when characteristics vary across the wafer surface.
Innovation Solution
A sub-sampling scheme combined with smart interpolation methods, such as wavelet analysis or neural network interpolation, allows for fewer measurements while approximating process tool correctables across the entire wafer, improving throughput and accuracy by determining an optimized set of measurement locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If metrology measurements are performed at one location or a limited number of locations on the wafer, then the measurement speed is improved, but the accuracy of process monitoring and control deteriorates
Solution Approach 1:
The wafer surface is divided into multiple regions (e.g., center, mid-ring, outer ring) with different sampling densities. The optimized sampling scheme segments the measurement locations into different zones, allowing faster measurements at critical regions while maintaining adequate coverage across the entire wafer surface, thus resolving the contradiction between measurement speed and accuracy.
Solution Approach 2:
Different regions of the wafer are assigned different measurement qualities or densities based on their importance. Critical regions receive higher measurement density while less critical regions use lower density, creating a non-uniform sampling scheme that improves overall accuracy without requiring full-wafer measurement at maximum density, thereby balancing speed and precision.
2Measurement precision
If metrology measurements are performed at all locations on the wafer, then the accuracy of process monitoring is improved, but the measurement time increases
Solution Approach 1:
Instead of measuring all locations on the wafer, the invention applies partial action by selecting only the most informative measurement locations using an optimized sampling scheme. This partial sampling approach, combined with interpolation techniques, provides sufficient accuracy for process monitoring without the time cost of complete wafer coverage, effectively resolving the time-accuracy tradeoff.
Solution Approach 2:
The measurement data from sampled locations is used to create a representative model or copy of the entire wafer's characteristic distribution. Through interpolation and modeling, the partial measurement data is extended to estimate conditions across unsampled regions, providing comprehensive process monitoring information without requiring complete physical measurement of all locations.
3Ease of operation
If fixed sampling locations are used for metrology measurements, then the simplicity of the measurement process is improved, but the ability to detect wafer-wide variations deteriorates
Solution Approach 1:
The sampling scheme transitions from a static fixed pattern to a dynamic optimized pattern that adapts to the specific wafer and process conditions. The measurement locations are dynamically selected based on wafer characteristics, process step, and identified variation patterns, allowing the system to maintain simplicity while capturing wafer-wide variations that fixed schemes miss.
Solution Approach 2:
The sampling parameters (locations, density, distribution) are changed from fixed values to optimized values based on process conditions and wafer characteristics. This parameter optimization allows the measurement process to remain simple to execute while adapting to different scenarios, thereby capturing essential wafer-wide variations without complicating the measurement procedure.
Data Source
Figure 1A~1B
Figure 2
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AI summary
The present invention may include performing a first measurement on a wafer of a first lot of wafers via an omniscient sampling process, calculating a first set of process tool correctables utilizing one or more results of the measurement performed via an omniscient sampling process, randomly selecting a set of field sampling locations of the wafer of a first lot of wafers, calculating a second set of process tool correctables by applying an interpolation process to the randomly selected set of field sampling locations, wherein the interpolation process utilizes values from the first set of process tool correctables for the randomly selected set of field sampling locations in order to calculate correctables for fields of the wafer of the first lot not included in the set of randomly selected fields, and determining a sub-sampling scheme by comparing the first set of process tool correctables to the second set of correctables.