Wafer Image Neural Networks for Pre-Fabrication Yield Prediction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor fabrication processes face challenges in identifying defects on wafers that can degrade device performance and reduce yield, as traditional methods struggle to predict electrical responses before device fabrication.
Innovation Solution
A neural network-based method analyzes wafer images and electrical data from previous devices to predict the electrical performance of future devices, using a multi-layer convolutional neural network to identify structural features that affect device yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional defect inspection methods are used, then defects can be identified, but the ability to predict electrical performance before fabrication is limited
Solution Approach 1:
The patent performs wafer evaluation and defect detection before device fabrication begins. By analyzing wafer images and process data in advance, the system predicts electrical performance and identifies suitable fabrication areas prior to committing resources, thereby preventing information loss about device outcomes.
Solution Approach 2:
The patent introduces a machine learning model as an intermediary between traditional inspection methods and electrical performance prediction. The model processes wafer images, process parameters, and defect data to generate predictions about device electrical characteristics, bridging the gap between physical inspection and performance forecasting.
2Productivity
If comprehensive wafer analysis is performed, then device yield can be improved, but processing time and complexity increase
Solution Approach 1:
The system performs comprehensive wafer analysis including imaging, defect detection, and machine learning-based prediction before fabrication. This preliminary evaluation identifies optimal fabrication areas and predicts yield outcomes, enabling better decision-making without adding complexity to the actual fabrication process.
Solution Approach 2:
The patent creates a multi-functional evaluation system that simultaneously performs defect detection, area suitability assessment, and electrical performance prediction using the same set of wafer images and process data. This consolidates multiple analysis functions into a unified workflow, managing complexity through integration rather than multiplication.
3Measurement precision
If machine learning models are trained on extensive data, then prediction accuracy improves, but computational resources and training time increase
Solution Approach 1:
The patent employs transfer learning where a pre-trained machine learning model is fine-tuned on semiconductor-specific data. This approach uses partial retraining on domain-specific datasets rather than training from scratch, achieving high prediction accuracy while significantly reducing training time and computational resources compared to comprehensive training.
Solution Approach 2:
The system prepares and curates training datasets in advance, organizing wafer images, process parameters, and corresponding electrical test results into structured formats. This preliminary data preparation enables efficient model training and iteration, reducing the time required for subsequent model development and refinement.
Data Source
AI summary
A computer-implemented method for evaluating a semiconductor wafer. In accordance with the present invention, using a properly designed neural network, the computer can take image data regarding the wafer at issue, plus image and electrical data regarding a prior wafer and devices fabricated on the prior wafer, to find relations to and between structural features, both known and previously unidentified, that can degrade the performance of devices fabricated on the wafer and/or can reduce the device yield of the wafer.