Wafer Bonding Alignment Through Back-Side Marks and Offset Mapping
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Solution Overview
Problem
The semiconductor industry faces challenges in aligning semiconductor devices during bonding processes, particularly when front-side alignment marks are not directly visible, leading to misalignment issues and reduced manufacturing efficiency.
Innovation Solution
The use of both front-side and back-side alignment marks, with a predetermined offset, allows for the detection and alignment of front-side marks using back-side marks, even when the front-side marks are not directly visible, improving alignment accuracy and efficiency by determining the location of front-side marks relative to back-side marks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If front-side alignment marks are used for bonding alignment, then alignment accuracy is improved, but visibility and detectability of the alignment marks deteriorates when they are not directly visible
Solution Approach 1:
The patent introduces back-side alignment marks as an intermediary solution. These marks are placed on the back side of the wafer where they are directly visible and detectable. A computational model establishes a geometric relationship between the front-side alignment marks (which are not directly visible) and the back-side alignment marks, allowing the system to use the visible back-side marks as a mediator to achieve alignment of the invisible front-side marks.
2Productivity
If direct bonding of wafers is performed, then manufacturing efficiency is improved, but alignment precision deteriorates when alignment marks are not directly visible
Solution Approach 1:
The patent implements preliminary action by pre-establishing a computational model that defines the geometric relationship between front-side and back-side alignment marks before the bonding process. This model is created during wafer fabrication, allowing the bonding system to directly use back-side mark detection for alignment without requiring complex real-time imaging of front-side marks, thus maintaining high manufacturing efficiency while achieving precise alignment.
3Device complexity
If traditional alignment methods using only front-side marks are used, then alignment process is simplified, but manufacturing efficiency deteriorates due to inability to directly detect front-side marks
Solution Approach 1:
The patent transitions from a two-dimensional alignment approach (using only front-side marks in the bonding plane) to a three-dimensional approach by incorporating back-side alignment marks. This adds a new dimension (the back side of the wafer) that is directly accessible and visible, allowing the alignment system to operate efficiently without increasing process complexity.
Data Source
AI summary
A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.