Wafer-on-Wafer Driver IC Segmentation for Display Miniaturization
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Solution Overview
Problem
Current display devices face challenges in miniaturization, image data loss minimization, and wiring reduction for driver integrated circuits (ICs), which affect the efficiency and quality of display panels.
Innovation Solution
A driver IC is designed with a wafer-on-wafer process, dividing circuits into two ICs that are combined using methods like wire bonding or flip-chip bonding, featuring a first IC for data processing, a second IC for sampling and conversion, and minimizing wire connections between them to enhance miniaturization and data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If driver IC is miniaturized, then display device bezel size is reduced, but image data loss increases
Solution Approach 1:
The driver IC is divided into two separate ICs: a first IC containing a first circuit for data processing, and a second IC containing second and third circuits for sampling and conversion. This segmentation allows optimization of each IC's function and reduces the total area while maintaining data integrity through dedicated functional blocks.
Solution Approach 2:
A buffer circuit is introduced as an intermediary between the first circuit (on first IC) and the second circuit (on second IC). This buffer minimizes signal degradation and data loss during transmission between the segmented ICs, enabling miniaturization without compromising image quality.
2Volume of moving object
If driver IC is miniaturized, then manufacturing cost is reduced, but wiring complexity increases
Solution Approach 1:
Multiple functional circuits are integrated onto two compact ICs using advanced packaging techniques (wafer-on-wafer, chip-on-glass, or chip-on-film). This merging approach consolidates what would otherwise require extensive external wiring into tightly coupled integrated structures, reducing overall wiring complexity despite the segmented architecture.
Solution Approach 2:
The patent employs three-dimensional packaging methods such as wafer-on-wafer bonding, chip-on-glass, or chip-on-film configurations. These techniques stack circuits vertically or arrange them in multi-layer structures, transforming two-dimensional wiring layouts into three-dimensional arrangements that reduce wire length and connection complexity.
3Productivity
If driver IC is miniaturized using wafer-on-wafer process, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The first and second ICs are designed with pre-configured bonding interfaces and alignment features before the wafer-on-wafer process. This preliminary preparation includes defining precise bonding pad locations, alignment marks, and connection geometries, which enables high-speed automated bonding while maintaining the required precision for miniaturized structures.
Data Source
AI summary
A driver integrated circuit (IC) according to one embodiment of the present disclosure includes a first IC, a second IC that is combined with the first IC, a first circuit configured to receive first image data, and generate second image data by correcting the first image data, a second circuit configured to sample the second image data, and a third circuit configured to convert the sampled second image data into a source signal, wherein the first circuit is mounted on the first IC, the second circuit is mounted on one of the first IC and the second IC, and the third circuit is mounted on the second IC.