Wafer-Level Optical Coupler Testing Without Wafer Dicing
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Solution Overview
Problem
Current methods for wafer level testing of adiabatic couplers require dicing the wafer, which is time-consuming and costly, and may result in improperly functioning couplers due to inadequate wafer processing.
Innovation Solution
A system and method that involves forming cavities in the BEOL layer of the wafer to expose adiabatic couplers, and using an interposer with waveguides and a redirecting element to adiabatically couple optical signals into and out of the couplers for testing without dicing the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer dicing is performed to test adiabatic couplers, then testing can be conducted, but time and cost increase significantly
Solution Approach 1:
The patent forms cavities in the BEOL layer before dicing to expose adiabatic coupler outputs. This preliminary action allows optical testing to be performed on the complete wafer without requiring individual dicing of each device, thereby reducing time while maintaining testing capability
Solution Approach 2:
The patent introduces an interposer with waveguides as an intermediary component. The interposer couples to multiple adiabatic couplers simultaneously through the cavities, enabling parallel optical testing of multiple devices without dicing, thus resolving the time-cost contradiction
2Reliability
If wafer dicing is performed to test adiabatic couplers, then testing can be conducted, but cost increases significantly
Solution Approach 1:
The cavities are formed in the BEOL layer before dicing, allowing optical access to be established at the wafer level. This eliminates the need for costly post-dicing assembly and individual device handling, reducing manufacturing costs while maintaining testing capability
Solution Approach 2:
The patent merges multiple testing functions into a single wafer-level operation. By forming cavities that expose multiple adiabatic coupler outputs simultaneously and using an interposer to couple to multiple devices, the system combines parallel testing capability with cost-effective wafer-level processing
3Manufacturing precision
If improper wafer processing occurs, then adiabatic couplers may be damaged, but dicing is required to detect issues
Solution Approach 1:
The cavities are formed in advance to provide optical access to adiabatic coupler outputs before dicing. This allows non-destructive optical testing to detect processing defects early, reducing the need for complex post-dicing inspection procedures
Solution Approach 2:
The patent replaces mechanical dicing-based inspection with optical testing through the cavities. Optical signals can traverse the adiabatic couplers and be detected through the interposer, providing a non-contact, non-destructive method to verify wafer processing quality without complex mechanical handling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables wafer level testing of adiabatic couplers and other optical components without dicing the wafer, reducing time and cost, and allowing for the verification of proper wafer processing.
Implementation Method 1
The at least one waveguide may be configured to adiabatically couple at least one optical signal out of the multiple ICs
Implementation Method 2
The redirecting element may be configured to receive the at least one optical signal from the at least one waveguide. The redirecting element may also be configured to vertically redirect the at least one optical signal towards the transparent layer
Implementation Method 3
The transparent layer may be configured to permit optical signals to pass through
Data Source
AI summary
A system may include a wafer that includes ICs and defines cavities. Each cavity may be formed in a BEOL layer of the wafer and proximate a different IC. The system may also include an interposer that includes a transparent layer configured to permit optical signals to pass through. The interposer may also include at least one waveguide located proximate the transparent layer. The at least one waveguide may be configured to adiabatically couple at least one optical signal out of the multiple ICs. Further, the interposer may include a redirecting element optically coupled to the at least one the waveguide. The redirecting element may be located proximate the transparent layer and may be configured to receive the at least one optical signal from the at least one waveguide. The redirecting element may also be configured to vertically redirect the at least one optical signal towards the transparent layer.