Wafer Ring Oscillator Circuit for Isolated FEOL and BEOL Capacitance
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Solution Overview
Problem
The measurement of effective capacitance in ring oscillator circuits is inaccurate due to the influence of short-current and parasitic capacitance from the front-end-of-line (FEOL) and back-end-of-line (BEOL) portions of semiconductor wafers, which complicates the evaluation of frequency response.
Innovation Solution
A test circuit with a clock generator that generates non-overlapping clock signals to eliminate short currents and a capacitance test circuit that measures effective capacitance by disconnecting FEOL and BEOL portions, allowing for individual characterization of capacitances from both layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If effective capacitance is measured using conventional ring oscillator circuits, then frequency response can be monitored, but measurement precision deteriorates due to short-current and parasitic capacitance interference
Solution Approach 1:
The invention divides the capacitance measurement into separate components by creating distinct test circuits for FEOL capacitance and BEOL capacitance. The FEOL test circuit measures capacitance before BEOL processing, while the BEOL test circuit measures capacitance after BEOL processing, allowing independent characterization and elimination of parasitic effects from each layer.
Solution Approach 2:
The invention extracts and measures parasitic capacitance components separately from the total capacitance. By measuring FEOL capacitance first and then measuring total capacitance after BEOL processing, the BEOL parasitic capacitance can be extracted by subtraction, eliminating its interfering effect on the intrinsic device capacitance measurement.
2Reliability
If ring oscillator circuits are used for monitoring device parameters, then frequency response evaluation is enabled, but measurement precision worsens due to short-current influence
Solution Approach 1:
The invention introduces separate test circuits as intermediary measurement structures that isolate the parasitic capacitance and short-current effects from the main device under test. These test circuits include dedicated capacitors and switches that allow measurement of parasitic effects without affecting the operation of the actual device parameters being monitored.
3Device complexity
If total capacitance is measured without separating FEOL and BEOL contributions, then measurement simplicity is maintained, but measurement precision deteriorates due to inability to isolate parasitic capacitance
Solution Approach 1:
The measurement system is segmented into multiple independent test circuits, each designed to measure specific capacitance components. The FEOL test circuit measures front-end capacitance, while the BEOL test circuit measures back-end capacitance, allowing systematic separation and characterization of parasitic effects from different processing stages.
Data Source
AI summary
A device for measuring characteristics of a wafer is provided. The device includes a first circuit on the wafer and having a first number of parallelly connected oscillators, and a second circuit on the wafer and having the first number of parallelly connected oscillators; wherein a first portion of the second circuit is disconnected from a second portion of the second circuit.