Wafer Overlay Correction Model Using Subset Mark Segmentation
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Solution Overview
Problem
Current semiconductor wafer processing techniques face challenges with overlay errors due to non-uniformity and deformation, leading to misalignment of patterns across layers, which are costly to correct and time-consuming to measure, especially with the need for smaller and denser structures that require tighter tolerances.
Innovation Solution
A method for calculating an overlay model using a subset of first and second overlay marks to estimate deviations, allowing for process correction parameters to be derived, which are then used to align and expose semiconductor wafers more efficiently by interpolating from a limited set of measured marks, reducing the need for extensive overlay measurements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If overlay measurements are performed on all overlay marks to ensure precision, then measurement accuracy is improved, but measurement time and cost increase significantly
Solution Approach 1:
The patent divides the overlay marks into two groups: a first group of overlay marks that are measured to obtain measurement data, and a second group of overlay marks that are not measured. This segmentation allows the system to achieve sufficient measurement precision while significantly reducing measurement time and cost by only measuring a subset of the total overlay marks.
Solution Approach 2:
The patent creates a virtual model of wafer deformation based on measurements from the first group of overlay marks. This model is then used to estimate overlay deviations for the second group of overlay marks, effectively copying the deformation pattern across the entire wafer surface without physically measuring every mark.
2Reliability
If all overlay marks are measured to achieve complete overlay error detection, then overlay error detection capability is improved, but measurement complexity increases
Solution Approach 1:
The patent uses a wafer deformation model created from limited measurements to estimate overlay deviations across the entire wafer surface. This modeling approach maintains reliable overlay error detection capability while significantly reducing measurement complexity by avoiding the need to measure every overlay mark.
Solution Approach 2:
The patent introduces a wafer deformation model as an intermediary between the measured overlay marks and the unmeasured overlay marks. This model acts as a mediator that translates local measurements into global overlay deviation estimates, simplifying the overall measurement system.
3Manufacturing precision
If extensive overlay measurements are performed to maintain precision with tighter tolerances, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent segments the overlay marks into measured and unmeasured groups, allowing the system to maintain manufacturing precision through modeling while improving productivity by reducing the number of physical measurements required. This enables faster processing without sacrificing alignment quality.
Solution Approach 2:
The patent performs preliminary measurements on a subset of overlay marks and creates a deformation model in advance. This preliminary action provides sufficient information for correction, eliminating the need for time-consuming comprehensive measurements and thereby improving wafer processing throughput.
Data Source
AI summary
A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.