Wafer Geometry Overlay Error Decomposition for Lithography Control
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Solution Overview
Problem
Conventional overlay correction processes in semiconductor manufacturing are limited by their inability to account for wafer geometry variations, leading to suboptimal scanner corrections and misalignments due to the lack of awareness about geometry changes, resulting in ineffective overlay error management.
Innovation Solution
A method and system that decompose wafer geometry-induced overlay errors into components such as common process signatures, lot-to-lot variations, and wafer-to-wafer variations, using a cascading analysis process to determine effectiveness factors for overlay correction, enabling improved measurement and prediction accuracies and optimized correction strategies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional overlay correction processes are used without accounting for wafer geometry variations, then the correction process is simple and fast, but the overlay correction precision and accuracy deteriorate
Solution Approach 1:
The patent segments wafer geometry-induced overlay errors into distinct components (common process signatures, lot-to-lot variations, wafer-to-wafer variations) using a cascading analysis process. This segmentation allows each component to be measured and corrected separately, improving overlay correction precision while managing complexity through systematic decomposition of the correction task.
Solution Approach 2:
The patent changes the parameters of the correction process by introducing geometry-based correction parameters derived from measuring wafer shape, thickness, and stress distributions. These parameter changes enable the correction system to adapt to specific wafer geometry variations, thereby improving overlay correction precision beyond conventional fixed-parameter approaches.
2Manufacturing precision
If wafer geometry variations are measured and accounted for in overlay correction, then overlay correction accuracy improves, but the measurement and processing time increase
Solution Approach 1:
The patent performs preliminary measurements of wafer geometry parameters (shape, thickness, stress) before the overlay correction process. By obtaining these geometry characteristics in advance, the system can pre-calculate correction factors and prepare correction strategies beforehand, reducing the time required during actual overlay correction while maintaining high alignment accuracy.
Solution Approach 2:
The patent implements a feedback mechanism where measured wafer geometry variations are continuously fed into the correction process. The system measures geometry, calculates corrections, applies corrections, and uses the results to refine subsequent measurements and corrections. This closed-loop feedback optimizes the balance between measurement time and alignment accuracy by learning from previous measurements.
3Reliability
If comprehensive breakdown analysis of overlay errors is performed, then error source identification and correction effectiveness improve, but the analysis complexity and computational requirements increase
Solution Approach 1:
The patent applies segmentation by breaking down total overlay errors into distinct error sources (common process signatures, lot-to-lot variations, wafer-to-wafer variations) through cascading analysis. This segmentation enables reliable identification of specific error sources and their correction effectiveness while managing analysis complexity by treating each error component separately rather than analyzing all errors simultaneously.
Data Source
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AI summary
Systems and methods for providing improved measurements and predictions of geometry induced overlay errors are disclosed. Information regarding variations of overlay errors is obtained and analyzed to improve semiconductor processes as well as lithography patterning. In some embodiments, a cascading analysis process is utilized to breakdown the wafer geometry induced overlay into various components. The breakdown analysis may also be utilized to determine effectiveness factors for the various components, which in turn may improve the prediction accuracy of the impact of wafer geometry on wafer overlay. Furthermore, the measurements and/or predictions of the wafer geometry induced overlay errors may be utilized to provide overlay monitoring and correction solutions.