Semiconductor Wafer Oxidation Flatness Control
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Solution Overview
Problem
Current methods for treating semiconductor wafers, particularly for producing components with line widths of 65 nm or less, fail to achieve the required flatness and nanotopography, especially in the edge region, and do not ensure sufficient layer thickness homogeneity, leading to issues with SFQR max values, edge roll-off, and bond quality.
Innovation Solution
A method involving the oxidation of semiconductor wafers with a location-dependent oxidation rate, controlled by varying light intensity based on measured parameters, to correct height deviations and layer thickness variations across the entire surface, ensuring uniform material removal and improved flatness and homogeneity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional process sequence (sawing, lapping, wet chemical etching, stock removal polishing, final polishing) is used, then manufacturing simplicity is maintained, but flatness and nanotopography requirements for 65 nm line widths cannot be achieved
Solution Approach 1:
The patent changes the physical-chemical parameters of the treatment process by introducing a liquid crystal composition with specific molecular structures and properties. This composition modifies the surface characteristics through controlled interaction with the semiconductor wafer, achieving the required flatness and nanotopography by adjusting chemical composition parameters rather than adding complex mechanical processing steps
Solution Approach 2:
The patent uses a composite liquid crystal composition containing multiple components (cyclic carbonate, cyclic carboxylate, and specific liquid crystal molecules) that work synergistically. This composite material provides both the chemical etching action and the liquid crystal ordering effect needed to achieve precise surface flatness and nanotopography control
2Manufacturing precision
If PACE method is used, then flatness is improved, but device complexity increases due to vacuum requirements and additional cleaning steps
Solution Approach 1:
The patent replaces the mechanical vacuum-based PACE system with a liquid-phase chemical process. The liquid crystal composition is applied in liquid form and allows atmospheric pressure operation, eliminating the need for vacuum equipment, complex flow control systems, and extensive cleaning infrastructure while achieving comparable or superior flatness results
3Manufacturing precision
If scanning method is used, then treatment is applied, but productivity decreases and edge roll-off problems occur
Solution Approach 1:
The patent merges the treatment function into a single liquid-phase application step that covers the entire wafer surface simultaneously. The liquid crystal composition is applied as a uniform layer that undergoes phase transition and chemical interaction across the whole surface at once, combining etching, flattening, and nanotopography control into one integrated process step rather than sequential scanning operations
4Productivity
If edge exclusion is reduced for partial sites, then more circuits can be integrated, but flatness control becomes more difficult
Solution Approach 1:
The patent achieves uniform treatment across different wafer regions by using a liquid crystal composition that maintains consistent molecular ordering and chemical reactivity from center to edge. The composition's specific molecular structure and properties ensure that the same treatment effect is achieved uniformly across the entire surface, including partial sites at the edges, without requiring region-specific parameter adjustments
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves improved flatness and nanotopography, with SFQR max values of 0.05 μm or less and edge roll-off of 0.2 μm or less, and layer thickness homogeneity of 1% or less, suitable for producing high-quality semiconductor wafers and SOI wafers with enhanced edge exclusion and reduced manufacturing costs.
Implementation Method 1
treating a semiconductor wafer by oxidizing at least one of the surfaces of the semiconductor wafer and removing the oxide layer
Implementation Method 2
The rate of oxidation reactions can be accelerated by irradiating light of a suitable wavelength
Data Source
Figure 1~2
Figure 3~4
AI summary
The invention relates to a method for treating a semiconductor wafer, comprising the following steps: a) spatially dependent measurement of a parameter characterizing the semiconductor wafer (5) in order to determine the spatially dependent value of this parameter over an entire surface of the semiconductor wafer (5), b) oxidation of this entire surface of the semiconductor wafer (5) under the influence of an oxidizing agent in the oxidation chamber (6) and simultaneous exposure of this entire surface to light sources (2), wherein the oxidation rate and thus the thickness of the resulting oxide layer depends on the light intensity at the surface of the semiconductor wafer (5), and c) removal of the oxide layer, wherein the light intensity in step b) is spatially predetermined.that the differences in the location-dependent values of the parameter measured in step a) are reduced by the location-dependent oxidation rate resulting from the location-dependent light intensity in step b) and the subsequent removal of the oxide layer in step c). The invention also relates to a device for carrying out the method according to the invention.