Wafer-to-Wafer Oxide Bonding for Precise 3D IC Overlay Alignment
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Solution Overview
Problem
Existing wafer-to-wafer bonding methods, such as oxide bonding and metal-to-metal bonding, are inadequate in achieving optimal integration density and reliability in 3D integrated circuits due to high processing temperatures and pressures, and lack efficient overlay control during alignment.
Innovation Solution
A method involving silicon-on-insulator technology to reduce wafer thickness through hydrogen implantation and separation, followed by oxide bonding without metal-to-metal bonding, enabling optical alignment from the bottom surface for improved overlay control and simplified manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If metal-to-metal bonding using thermo-compression bonding is used, then bonding strength is improved, but processing temperature and pressure requirements increase
Solution Approach 1:
The patent changes the bonding parameters from high temperature and pressure (thermo-compression bonding) to low temperature and pressure (oxide bonding). By using oxide layers as the bonding interface instead of metal-to-metal contact, the bonding process can be performed at significantly reduced temperature and pressure conditions while still achieving adequate bonding strength for 3D IC applications.
Solution Approach 2:
The patent introduces oxide layers as an intermediary bonding interface between wafers. Instead of directly bonding metal surfaces together which requires high energy input, the oxide layers serve as a mediator that enables bonding at lower temperatures and pressures. The oxide-to-oxide bonding mechanism provides a more gentle bonding process while maintaining structural integrity.
2Reliability
If traditional wafer bonding methods are used, then bonding is achieved, but overlay control precision deteriorates
Solution Approach 1:
The patent enables optical alignment from the bottom surface of wafers by using oxide bonding that allows light transmission. This dimensional change in the alignment approach (aligning from bottom rather than top surface) provides better access to alignment marks and improves overlay control precision while maintaining bonding reliability through the oxide bonding mechanism.
3Temperature
If oxide bonding is used, then processing temperature is reduced, but bonding strength may be insufficient
Solution Approach 1:
The patent optimizes oxide layer parameters (thickness, composition, density) to achieve adequate bonding strength at low temperatures. By carefully controlling the oxide layer properties and bonding pressure, the patent demonstrates that oxide-to-oxide bonding can provide sufficient bonding strength for 3D IC applications without requiring high temperature processing.
4Reliability
If complex bonding processes are used, then bonding reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent extracts and eliminates complex process steps from traditional bonding methods. By using oxide bonding instead of thermo-compression bonding or hybrid bonding, the patent removes the need for high temperature and pressure equipment, complex alignment systems, and multiple bonding stages, thereby simplifying the manufacturing process while maintaining adequate bonding reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances process yield and product reliability by allowing precise alignment and reducing manufacturing complexity, resulting in improved integration density and performance of 3D integrated circuits.
Implementation Method 1
The substrate is further subjected to an ion implantation process to form an etch stop layer in the substrate
Implementation Method 2
oxidet bonding or fusion bonding, metal-to-metal bonding using thermo-compression bonding
Data Source
AI summary
A method of forming a semiconductor structure is provided. Two wafers are first bonded by oxide bonding. Next, the thickness of a first wafer is reduced using an ion implantation and separation approach, and a second wafer is thinned by using a removal process. First devices are formed on the first wafer, and a carrier is then attached over the first wafer, and an alignment process is performed from the bottom of the second wafer to align active regions of the second wafer for placement of the second devices with active regions of the first wafer for placement of the first devices. The second devices are then formed in the active regions of the second wafer. Furthermore, a via structure is formed through the first wafer, the second wafer and the insulation layer therebetween to connect the first and second devices on the two sides of the insulation layer.