Wafer-Level Chip Package Sidewall Shielding Against Die Chipping
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Solution Overview
Problem
Wafer level chip scale packages (WLCSPs) face handling defects such as die corner stress, chipping, and cracks due to the lack of sidewall protection during manufacturing and usage, especially as demand increases for smaller and thinner dies.
Innovation Solution
A wafer level chip scale package design that includes a bare silicon die with a backside tape adhered using an adhesive layer, which protrudes beyond the sidewall surfaces and wraps around the corners, providing protection against damage during handling and physical stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the die size is reduced to meet smaller and thinner requirements, then the package dimensions are reduced, but the die becomes more susceptible to corner damage and chipping during handling
Solution Approach 1:
The patent applies beforehand cushioning by providing sidewall protection structures (such as molding compound or separate protective elements) that are in place before the die corners can be damaged during handling. This protective layer acts as a cushion that absorbs mechanical stress and prevents corner chipping and cracking, allowing smaller dies to be handled safely without compromising reliability
2Length of moving object
If the die is made thinner to reduce package thickness, then the package profile is reduced, but the die sidewalls become more vulnerable to damage during manufacturing and usage
Solution Approach 1:
The patent employs composite materials by combining the thin die structure with protective sidewall materials (such as molding compound or specialized protective layers) that have higher mechanical strength. This composite structure allows the die to remain thin while the protective material reinforces the sidewalls against damage during manufacturing and usage
3Device complexity
If no sidewall protection is provided to simplify the structure, then the manufacturing process is simpler, but corner chipping and cracks occur during handling
Solution Approach 1:
The patent applies preliminary action by incorporating sidewall protection measures during the die attachment process itself, rather than requiring separate complex protection steps. The molding compound or protective elements are applied in advance to cover the die sidewalls and corners, preventing damage before it can occur during subsequent handling and assembly operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents sidewall damage and chipping, enhancing the reliability and yield of WLCSPs by providing structural support and protection during processing and environmental stresses.
Implementation Method 1
A backside tape is adhered to the rear surface by using an adhesive layer
Data Source
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AI summary
A wafer level chip scale package (10) includes a bare silicon die (100) having an active surface (S1), a rear surface (S2) opposite to the active surface (S1), and a sidewall surface (SW) between the active surface (S1) and the rear surface (S2). The bare silicon die (100) includes a backside corner (BC) between the rear surface (S2) and the sidewall surface (SW). A plurality of pads (101) is disposed on the active surface (S1). A plurality of conductive elements (110) is disposed on the plurality of pads (101), respectively. A backside tape (220) is adhered to the rear surface (S2) by using an adhesive layer (210). The adhesive layer (210) and the backside tape (220) protrude beyond the sidewall surface (SW) of the bare silicon die (100). The adhesive layer (210) extends along the sidewall surface (SW) and wraps around the backside corner (BC).