Wafer-Level Semiconductor Package With Direct Bonded Multi-Die Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of integrated circuit packages with multiple device dies poses challenges in manufacturing cost, process steps, and design flexibility, particularly in achieving efficient electrical connections and reduced package size.
Innovation Solution
The method involves direct bonding of wafers and semiconductor devices using dielectric-to-dielectric, metal-to-metal, or hybrid bonding techniques, forming through-substrate vias, and encapsulating with a molding compound to create wafer packages that allow for reduced process costs, time, and improved design flexibility, while enabling finer bump pitches and higher density interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple device dies are packaged in the same package to achieve more functions, then device performance and functionality are improved, but manufacturing complexity and process steps increase
Solution Approach 1:
The package is divided into multiple device dies (processors, memory cubes, I/O devices) that are independently manufactured and then bonded together. Each die can be optimized separately for its specific function while maintaining overall system integration, thus improving versatility without proportionally increasing manufacturing complexity.
Solution Approach 2:
Multiple device dies with different functions are combined into a single package structure through direct bonding. This merging approach allows diverse functionalities to coexist in one package while using standardized bonding processes, thereby improving adaptability without linearly increasing manufacturing complexity.
2Ease of manufacture
If device dies are bonded to the same device die to form a system, then manufacturing cost is saved, but bonding precision and alignment requirements increase
Solution Approach 1:
An intermediary bonding layer or bonding pad structure is used between device dies to facilitate alignment and bonding. This intermediary element provides a standardized interface that simplifies the bonding process and reduces precision requirements while maintaining cost effectiveness.
Solution Approach 2:
The bonding process utilizes controlled parameters such as temperature, pressure, and bonding material properties to achieve reliable connections. By optimizing these parameters, the bonding precision requirement is reduced while maintaining manufacturing cost efficiency.
3Reliability
If through-silicon vias are used for electrical connection, then electrical connectivity is improved, but manufacturing complexity and defect risk increase
Solution Approach 1:
Through-silicon vias are formed and prepared in advance before the final bonding process. This preliminary action allows for quality control and inspection before assembly, ensuring electrical connectivity while managing manufacturing complexity through staged processing.
Solution Approach 2:
The via formation process utilizes controlled parameters such as etch depth, via diameter, and filling material properties to optimize electrical connectivity. By carefully managing these parameters, reliable electrical connections are achieved while minimizing the increase in manufacturing complexity.
4Use of energy by moving object
If direct bonding is used instead of solder connections, then power consumption is reduced, but bonding process requirements and material compatibility challenges increase
Solution Approach 1:
The traditional solder-based mechanical and thermal bonding system is replaced with a direct bonding system that relies on diffusion bonding or direct metal-to-metal contact. This substitution eliminates the need for solder materials and associated reflow processes, reducing power consumption while managing bonding process requirements through controlled bonding conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in smaller form-factor packages with improved mechanical and electrical performance, reduced defects, and increased yield by enabling direct chip-to-wafer bonding without solder connections, facilitating shorter die-to-die interconnections and lower power consumption.
Implementation Method 1
directly bonding a first wafer to a second wafer, the bonding electrically connecting a first interconnect structure of the first wafer to a second interconnect structure of the second wafer; directly bonding first semiconductor devices to the second wafer
Implementation Method 2
directly bonding a first wafer to a second wafer, the bonding electrically connecting a first interconnect structure of the first wafer to a second interconnect structure of the second wafer
Data Source
AI summary
A method includes directly bonding a first wafer to a second wafer, wherein the bonding electrically connects a first interconnect structure of the first wafer to a second interconnect structure of the second wafer; directly bonding first semiconductor devices to the second wafer, wherein the bonding electrically connects the first semiconductor devices to the second interconnect structure; encapsulating the first semiconductor devices with a first encapsulant; and forming solder bumps over the first semiconductor devices.