Wafer-Level Package Layout Using LDS Interconnects for High Pin Count
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Solution Overview
Problem
Existing wafer-level packaging techniques face challenges such as high cost, large size, and space consumption due to the use of solder balls, particularly in forming high density, large size, and high pin-count packages, and are difficult to form with multiple integrated circuit dies.
Innovation Solution
The method involves adhesively attaching integrated circuit dies, forming a laser direct structuring (LDS) activatable layer, activating and metallizing desired patterns to create conductive areas, and singulating the wafer to form wafer-level packages with interconnected dies, using a redistribution layer and solder balls for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional wafer level packaging techniques are used, then packages can be formed with integrated circuit dies, but the cost is high and the package size is large
Solution Approach 1:
The patent merges multiple functions into the molding compound: it serves as both the encapsulation material and the substrate for the redistribution layer. The LDS activatable layer is integrated directly into the molding compound, eliminating the need for separate substrate and encapsulation layers, thereby reducing overall package size and material cost
Solution Approach 2:
The patent transitions from planar circuit board mounting to three-dimensional wafer-level integration. Multiple integrated circuit dies are stacked vertically and interconnected through the molding compound, enabling high-density packaging in a compact volume by utilizing the vertical dimension
2Reliability
If solder balls are used to connect multiple integrated circuit dies, then electrical connections are established, but space is consumed and cost increases
Solution Approach 1:
The patent extracts the interconnection function from traditional solder balls and implements it through conductive traces formed directly within the molding compound using LDS technology. This eliminates the need for discrete solder ball components, reducing space consumption while maintaining reliable electrical connections
Solution Approach 2:
The molding compound acts as an intermediary medium that simultaneously provides mechanical support, electrical interconnection, and encapsulation. The LDS activatable layer within the molding compound creates conductive pathways that mediate the electrical connection between stacked dies, replacing the traditional solder ball intermediary
3Adaptability or versatility
If high density, large size, and high pin-count packages are formed, then functionality is improved, but manufacturing cost increases
Solution Approach 1:
The molding compound is designed to perform multiple functions: encapsulation of dies, substrate for mounting additional components, and carrier for the redistribution layer. The LDS activatable layer provides universal conductivity patterns that can be customized for different pin-count requirements without changing the basic package structure, enabling cost-effective high-density packaging
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces costs and space consumption by enabling compact, high-density packages with efficient electrical connections between integrated circuits, facilitating the integration of passive components and chips.
Implementation Method 1
forming a laser direct structuring (LDS) activatable layer over the front sides of the first integrated circuits and the second integrated circuits... activating portions of the LDS activatable layer to form desired patterns of structured areas within the LDS activatable layer
Implementation Method 2
metallizing the desired patterns of structured areas to form conductive areas within the LDS activatable layer, some of the formed conductive areas electrically connecting the pads of the first integrated circuits to the pads of the second integrated circuits
Implementation Method 3
adhesively attaching back sides of second integrated circuits to a front side of the wafer including a plurality of first integrated circuits
Data Source
AI summary
Described herein is a method of forming wafer-level packages from a wafer. The method includes adhesively attaching front sides of first integrated circuits within the wafer to back sides of second integrated circuits such that pads on the front sides of the first integrated circuits and pads on front sides of the second integrated circuits are exposed. The method further includes forming a laser direct structuring (LDS) activatable layer over the front sides of the first integrated circuits and the second integrated circuits and over edges of the second integrated circuits, and forming desired patterns of structured areas within the LDS activatable layer. The method additionally includes metallizing the desired patterns of structured areas to form conductive areas within the LDS activatable layer.