Wafer-Level Package Trench Layout for Underfill Flow and Warpage
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Solution Overview
Problem
Semiconductor packages face challenges in achieving high performance, large capacity, and high reliability while being compact and lightweight, particularly due to issues like warpage and defects in the underfill process, especially in fan-out wafer-level packages (FOWLPs) with low bump heights.
Innovation Solution
A wafer-level package design that incorporates a redistribution substrate with a trench structure, allowing the underfill to efficiently fill the space between the substrate and the semiconductor chip, minimizing warpage and preventing overflow defects by using a capillary underfill process even with low bump heights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the bump height is reduced to achieve compact package design, then the package size and weight are reduced, but the underfill process becomes difficult and warpage increases
Solution Approach 1:
The invention divides the space between the substrate and semiconductor chip into two regions: a first region filled with underfill material and a second region (trench area) that guides the underfill flow. This segmentation allows the underfill to be delivered effectively even when bump heights are reduced, resolving the contradiction between compact package size and underfill process reliability.
Solution Approach 2:
The invention introduces a trench structure as an intermediary element between the substrate and semiconductor chip. This trench acts as a guide channel that facilitates underfill material flow into the gap space, enabling reliable underfill delivery without requiring high bump heights, thus maintaining underfill process reliability while allowing reduced package size.
2Stability of the object's composition
If the underfill is delivered to fill the space between substrate and chip, then warpage is reduced, but underfill overflow defects occur without proper structural control
Solution Approach 1:
The invention segments the gap space into a first region for underfill filling and a second trench region that controls underfill flow. This segmentation ensures that underfill material is directed precisely where needed while preventing overflow, achieving both warpage reduction through complete filling and manufacturing precision through controlled delivery.
Solution Approach 2:
The invention applies different structural qualities to different regions: the first region is designed for underfill accommodation and warpage reduction, while the second trench region is designed for flow control and precision delivery. This local differentiation of structural quality enables simultaneous achievement of warpage control and filling precision.
3Manufacturing precision
If a trench structure is added to control underfill flow, then underfill filling precision is improved, but device complexity increases
Solution Approach 1:
The invention implements a simple segmentation of the substrate surface into a first region and a second trench region. This segmentation provides effective underfill flow control and precision filling without requiring complex multi-layer or multi-component structures, thus improving manufacturing precision while minimizing increases in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces warpage and enhances reliability by ensuring complete filling of the underfill without defects, improving the overall performance and reliability of the semiconductor package.
Implementation Method 1
an underfill filling a space between the redistribution substrate and the semiconductor chip
Data Source
AI summary
Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.