Wafer-Level Package Structure for Warpage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor device packaging technologies face challenges in achieving efficient warpage control and cost-effective manufacturing processes, particularly in wafer level packaging, which affect the reliability and yield of integrated circuits.
Innovation Solution
A manufacturing method involving a carrier with a debond layer and solder resist layer, where conductive pillars and semiconductor dies are formed, encapsulated, and connected through a redistribution circuit structure, followed by planarization and debonding, to create a package structure with improved warpage control and reduced complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wafer level packaging is used to reduce manufacturing cost, then manufacturing cost decreases, but warpage control becomes difficult
Solution Approach 1:
The package structure is segmented into multiple functional layers including a substrate layer, a redistribution layer, and an encapsulant layer. This segmentation allows each layer to be optimized independently for cost-effectiveness while collectively achieving warpage control through the distributed structural design.
Solution Approach 2:
The patent employs composite material structures combining different materials with complementary properties - the substrate provides mechanical support, the redistribution layer offers electrical connectivity and stress management, and the encapsulant provides protection and dimensional stability. This composite approach enables simultaneous achievement of low cost and good warpage control.
2Manufacturing precision
If complex packaging processes are used to achieve better warpage control, then warpage control improves, but manufacturing complexity increases
Solution Approach 1:
The substrate and redistribution layer are designed and positioned in advance with pre-calculated geometries and material properties that inherently compensate for expected warpage during packaging. This preliminary design approach eliminates the need for complex real-time warpage correction processes during manufacturing.
Solution Approach 2:
The patent optimizes key parameters such as layer thicknesses, material coefficients of thermal expansion, and geometric dimensions to achieve warpage control within acceptable ranges. By carefully selecting and adjusting these parameters during the design phase, the manufacturing process becomes simpler while maintaining good warpage control.
3Reliability
If traditional packaging methods are used to ensure reliability, then reliability is maintained, but manufacturing cost increases
Solution Approach 1:
The package structure is designed to be self-supporting and self-aligning during the wafer level packaging process. The substrate and encapsulant are configured to automatically maintain proper positioning and structural integrity without requiring additional complex processing steps or expensive equipment, thereby achieving reliable packaging at lower cost.
Solution Approach 2:
The substrate serves multiple functions simultaneously: providing mechanical support, enabling electrical redistribution, managing stress and warpage, and facilitating thermal management. This multi-functionality eliminates the need for separate components and processes that would increase manufacturing cost while maintaining reliability.
Data Source
AI summary
A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.