Wafer-Level Semiconductor Packaging Barrier for Underfill Bleeding
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in preventing underfill bleeding at the edge of semiconductor wafers, which can compromise the reliability of the semiconductor structure.
Innovation Solution
The implementation of a first barrier structure, such as a polymer wall or conductive elements, is positioned between the second electrical connectors and the edge of the second surface mount components to hinder the spread of underfill, ensuring the semiconductor structure's integrity and reducing the risk of underfill bleeding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-level packaging is used to improve manufacturing efficiency, then productivity increases, but underfill bleeding at the wafer edge occurs compromising reliability
Solution Approach 1:
The patent applies preliminary action by forming a barrier structure at the wafer edge before the underfill application. This barrier structure pre-prevents the potential bleeding issue by creating a physical obstruction that stops underfill from reaching the wafer edge, thus resolving the contradiction between maintaining high productivity through wafer-level packaging and ensuring reliability by preventing underfill bleeding.
2Reliability
If barrier structure is added to prevent underfill bleeding, then reliability improves, but device complexity increases
Solution Approach 1:
The patent applies local quality by implementing the barrier structure only at the specific location where underfill bleeding occurs (the wafer edge), rather than modifying the entire packaging structure. This localized approach prevents underfill bleeding and improves reliability while minimizing the increase in overall device complexity, as the barrier is confined to a specific region rather than being a system-wide modification.
Data Source
AI summary
A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors.