Wafer Pad Alignment Test Circuit Using Resistance Ratio Detection
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Solution Overview
Problem
Existing technologies fail to accurately determine whether semiconductor wafers are aligned during the manufacturing process of semiconductor devices, which is crucial for yield and the three-dimensional structure of non-volatile memory devices.
Innovation Solution
A semiconductor multi-layer structure that includes a first semiconductor wafer with multiple pads, a second semiconductor wafer with corresponding pads, and a test circuit or scanner that applies voltages and performs electron beam scanning to compare the alignment of pads between the wafers based on resistance ratios and electron reflection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional alignment determination methods are used, then the manufacturing process is simple, but the alignment accuracy is insufficient
Solution Approach 1:
The patent introduces a test circuit as an intermediary system that includes voltage application units, resistance measurement units, and calculation units. This intermediary device mediates between the wafers to be aligned and the alignment determination process, enabling accurate alignment detection through resistance ratio measurements without requiring direct complex alignment mechanisms
Solution Approach 2:
The patent replaces conventional mechanical or optical alignment determination methods with an electrical measurement system. By applying voltages to pad combinations and measuring resistance ratios, the system substitutes mechanical alignment checks with electrical property-based determination, achieving higher precision through electrical field interactions rather than mechanical contact or optical visualization
2Measurement precision
If voltage application method is used, then alignment determination accuracy is improved, but energy consumption increases
Solution Approach 1:
The patent applies voltage only to specific pad combinations that are being tested for alignment, rather than applying voltage across the entire wafer surface. The voltage application is localized to the necessary measurement points (pad combinations), performing partial action only where alignment determination is needed, thus reducing overall energy consumption while maintaining measurement accuracy
Solution Approach 2:
The alignment determination process uses periodic voltage application and resistance measurement cycles. The test circuit applies voltage, measures resistance, calculates resistance ratios, and determines alignment in discrete periodic steps rather than continuous operation, allowing for energy efficiency by activating the measurement system only when alignment checks are required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution accurately determines the alignment of semiconductor wafers, ensuring successful combination and reducing misalignment errors, which is critical for the manufacturing of semiconductor devices, especially those with three-dimensional structures.
Implementation Method 1
a test circuit configured to apply a first voltage to a reference combination portion in which a preset first reference pad among the plurality of first pads is combined with a preset second reference pad among the plurality of second pads and apply a second voltage to a comparison combination portion in which at least one first pad among the plurality of first pads is combined with at least one second pad among the plurality of second pads, wherein the test circuit compares a voltage distributed based on a resistance ratio of the reference combination portion to the comparison combination portion
Implementation Method 2
a scanner configured to perform electron beam scanning of a reference combination portion in which a preset first reference pad among the plurality of first pads is combined with a preset second reference pad among the plurality of second pads and a comparison combination portion in which at least one first pad among the plurality of first pads is combined with at least one second pad among the plurality of second pads
Implementation Method 3
the scanner determines whether the at least one first pad is aligned with the at least one second pad based on the amount of electrons reflected from the reference combination portion and the comparison combination portion during the electron beam scanning
Data Source
AI summary
A semiconductor multi-layer structure includes a first semiconductor wafer including a plurality of first pads, a second semiconductor wafer including a plurality of second pads combined with the plurality of first pads, and a test circuit configured to apply a first voltage to a reference combination portion in which a preset first reference pad among the plurality of first pads is combined with a preset second reference pad among the plurality of second pads and apply a second voltage to a comparison combination portion in which at least one first pad among the plurality of first pads is combined with at least one second pad among the plurality of second pads, wherein the test circuit compares a voltage distributed based on a resistance ratio of the reference combination portion to the comparison combination portion with a preset reference voltage to determine whether the at least one first pad is aligned with the at least one second pad.