Semiconductor Wafer Pad Layout for Probe Contact Checking

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional wafer level burn-in testing methods face challenges in efficiently checking the contact state of probe needles due to wafer warpage and temperature changes, leading to increased defective product rates and reduced throughput, while existing contact check methods either fail to account for actual conditions or limit wafer design.

Innovation Solution

A semiconductor wafer design incorporating second pads with longer conductive portions for contact check, allowing flexible and efficient contact checking of probe needles without affecting element inspection areas, and optionally serving as flip-chip connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a contact check pattern with the same dimensions as chip pattern is prepared, then contact check of probe needles can be performed, but the pad area increases and limits the arrangement design of semiconductor elements

Engineering Contradiction:
Improvecontact check capabilityVSAvoidpad area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The pad structure is segmented into multiple regions: a first pad region for contact check and a second pad region for semiconductor element connection. This segmentation allows the contact check function to be separated from the element connection function, enabling compact design without compromising either function's effectiveness

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The pad structure is designed to serve multiple functions: it can be used for contact check of probe needles, for connection of semiconductor elements, and the conductive portion can extend to provide both contact check capability and element connection capability, reducing the need for separate dedicated areas

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If contact check is performed on a conductive substrate larger than wafer range, then contact failure with substrate can be checked, but it cannot check contact state under actual measurement conditions with wafer warpage and temperature changes

Engineering Contradiction:
Improvecontact state detectionVSAvoidadaptability to actual measurement conditions
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The contact check pad is prepared in advance on the wafer itself, with a conductive portion that extends beyond the chip pattern. This preliminary preparation allows the probe needles to be checked for contact state under conditions that closely simulate actual measurement environments, including wafer warpage and temperature variations, before actual element inspection

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The contact check pad structure copies the essential features of the chip pattern and element connection structure, allowing contact verification under realistic conditions. The conductive portion replicates the electrical connection characteristics of actual elements while providing extended contact area for reliable probe needle testing

Inventive Principle:
Principle #26Copying

3Productivity

If probe needles are used for inspection of semiconductor elements, then element characteristics can be evaluated, but contact failure of probe needles increases defective product rate and decreases throughput

Engineering Contradiction:
ImprovethroughputVSAvoiddefective product rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Contact check of probe needles is performed in advance before actual semiconductor element inspection. The extended conductive portion of the pad provides a dedicated contact check region that allows verification of probe needle contact state, ensuring only functional probe needles are used for element inspection, thereby reducing defective product rate and maintaining high throughput

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12474397B2Semiconductor wafer
Publication Date: 2025.11.18 NT T INC
  • US12474397B2 patent drawing
  • US12474397B2 patent drawing
  • US12474397B2 patent drawing

AI summary

This semiconductor wafer has formed therein a plurality of chips, each of which has incorporated therein a semiconductor element to be tested. The semiconductor wafer is characterized by comprising: first pads which are formed on the chips, and to which a plurality of probe needles are connected, the probe needles being connected to the semiconductor elements and used for testing the semiconductor elements; and a second pad that is used for performing a contact check on the probe needles, the second pad having a conductive section greater in length than the distance between the centers of the first pads.