Semiconductor Wafer Measurement Pad Layering
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing chip area due to the large area requirements of evaluation pads, which necessitate a more efficient configuration for characteristic evaluation devices and measurement pads.
Innovation Solution
The semiconductor device incorporates first and second characteristic evaluation devices with corresponding measurement pads in different layers of the interconnect layer, allowing for reduced chip area by overlapping measurement pads in plan view and providing separate pads for each evaluation device, thus avoiding issues of insufficient breakdown voltage and unidentified leakage paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple evaluation pads are provided for multiple characteristic evaluation devices, then electrical characteristics can be evaluated, but chip area increases
Solution Approach 1:
The patent applies dimensionality change by moving measurement pads from the same layer to different layers of the interconnect structure. Specifically, first measurement pads are formed in one interlayer insulating film layer while second measurement pads are formed in another layer, allowing vertical stacking that reduces planar area occupation while maintaining separate electrical evaluation paths for multiple characteristic evaluation devices
2Area of stationary object
If measurement pads are shared between evaluation devices, then chip area is reduced, but breakdown voltage becomes insufficient and leakage paths cannot be identified
Solution Approach 1:
The patent applies segmentation by providing separate first measurement pads and second measurement pads for different characteristic evaluation devices. These pads are formed in different layers, creating distinct electrical measurement paths that prevent interference between devices while maintaining adequate breakdown voltage levels and enabling accurate identification of leakage paths for each evaluation device
3Reliability
If multiple measurement pads are provided in the same layer, then electrical characteristics can be measured, but manufacturing complexity increases
Solution Approach 1:
The patent resolves manufacturing complexity by utilizing the vertical dimension of the interconnect structure. Instead of placing multiple measurement pads in the same horizontal layer, the invention distributes them across different interlayer insulating film layers, allowing standard multi-layer interconnect fabrication processes to be used without requiring complex same-layer routing
Data Source
AI summary
There is a room for improvement in conventional semiconductor devices in terms of reducing the chip area. A semiconductor device 1 comprises an evaluation transistor 10 (first characteristic evaluation device), an evaluation transistor (second characteristic evaluation device), measurement pads 30 (first measurement pads) and measurement pads 40 (second measurement pads). The measurement pad 30 and the measurement pad 40 are provided in different layers in the interconnect layer.