Wafer Panel Assembly Clamping via Connection Portion
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Solution Overview
Problem
The existing wafer level Chip Scale Package (CSP) technology faces inefficiencies due to the need for a conductive jig to clamp the wafer periphery, resulting in ineffective peripheral areas, uneven conductive layer distribution, and increased packaging costs, which limits its application.
Innovation Solution
A method involving the formation of a connection portion around the wafer to create a panel assembly, allowing for clamping on the connection member instead of the wafer periphery, and forming a dummy conductive layer to ensure uniform conductive layer properties, enabling simultaneous processing of multiple wafers and reducing ineffective areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a conductive jig is used to clamp the wafer periphery, then the wafer can be held and processed, but ineffective peripheral areas are created and conductive layer distribution becomes uneven
Solution Approach 1:
The patent introduces a connection portion as an intermediary element between the wafer and the clamping mechanism. This connection portion is formed around the periphery of the wafer and serves as the clamping target, allowing the conductive jig to clamp the connection portion instead of directly clamping the wafer. This resolves the contradiction by transferring the clamping action to a dedicated intermediate structure, preventing direct contact between the clamping mechanism and the wafer's active areas, thus avoiding ineffective peripheral areas and ensuring uniform conductive layer distribution on the wafer surface.
2Strength
If a conductive jig clamps the wafer periphery, then the wafer can be secured, but the peripheral area becomes ineffective for chip production
Solution Approach 1:
The patent segments the wafer structure by adding a separate connection portion around the periphery. This connection portion is distinct from the wafer's active chip area, allowing the clamping force to be applied to the connection portion while leaving the wafer's effective area intact. The segmentation principle resolves the contradiction by creating a dedicated peripheral structure that bears the mechanical stress of clamping, thereby preserving the maximum possible area of the wafer for chip production.
3Reliability
If multiple wafers are processed individually, then each wafer receives proper attention, but packaging efficiency is reduced
Solution Approach 1:
The patent merges multiple wafers into a panel assembly structure where multiple wafers are arranged and connected together with connection portions. This merging allows multiple wafers to be processed simultaneously in a single packaging operation, maintaining processing quality through the standardized connection portion design while dramatically improving packaging efficiency. The connection portions provide uniform clamping surfaces that ensure reliable processing across all wafers in the panel.
4Ease of operation
If the wafer periphery is used for clamping, then the wafer can be held, but packaging costs increase
Solution Approach 1:
The connection portion is formed in advance during the wafer fabrication process, before the packaging operation. This preliminary action creates ready-to-use clamping surfaces on the connection portions, eliminating the need for additional costly packaging equipment or complex handling mechanisms. By preparing the clamping interfaces beforehand as an integral part of the wafer structure, the patent reduces packaging costs while maintaining ease of operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach avoids the formation of ineffective areas, ensures uniform conductive layer properties, and significantly improves packaging efficiency by allowing multiple wafers to be processed simultaneously, thereby reducing costs and enhancing the effectiveness of the CSP technology.
Implementation Method 1
The conductive layer is formed using an electroplating process
Data Source
AI summary
The embodiments of the present disclosure relate to a packaging method, a panel assembly, a wafer package and a chip package. The semiconductor device packaging method includes: providing at least one wafer including a first surface and a second surface opposite to each other and a side surface connecting the first surface and the second surface, the first surface being an active surface; forming a connection portion on the side surface of the at least one wafer around the wafer, the wafer and the connection portion forming a panel assembly, the connection portion includes a third surface on the same side of the first surface of the wafer and a fourth surface on the same side as the second surface of the wafer, the third surface and the first surface forming a to-be-processed surface of the panel assembly; and forming a first dielectric layer on the first surface of the wafer. The packaging method of the embodiments of the present disclosure may improve packaging efficiency and utilization of a wafer.