Wafer Passivation Trench Dicing for Cleaner Semiconductor Chips
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Solution Overview
Problem
Current methods for producing display devices for augmented reality (AR) and virtual reality (VR) applications face challenges due to the use of long wires and metal interconnections, which consume space and complicate mounting, especially in smaller form factors.
Innovation Solution
A method involving forming an inter-metal dielectric (IMD) layer, an alternating stack, and a passivation layer on a wafer, followed by a dicing process along a scribe line to create a trench, which allows for efficient separation of the wafer into chips with dielectric and passivation layers on the top surface and sidewalls, reducing contamination and debris.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If long wires or metal interconnections are used to connect DDICs to display module, then the connection is achieved, but the space consumption increases and mounting difficulty increases
Solution Approach 1:
The patent transitions from planar wire connections to three-dimensional vertical stacking by forming alternating stacks of conductive and dielectric layers. This allows electrical connections to be established in the vertical dimension rather than requiring long horizontal wire runs, thereby reducing space consumption while improving mounting efficiency.
Solution Approach 2:
The patent implements nested structures by forming alternating stacks where conductive layers are embedded within dielectric layers. Multiple conductive pathways are nested vertically within the same footprint area, eliminating the need for extensive lateral wire routing and reducing overall device volume.
2Ease of manufacture
If dicing is performed before forming dielectric and passivation layers, then the dicing process is simplified, but contamination and debris increase
Solution Approach 1:
The patent performs the dicing process preliminarily before forming the dielectric and passivation layers. By establishing the scribe lines and performing dicing at this early stage, the subsequent dielectric and passivation layers can be formed to cover and protect the diced surfaces, preventing contamination and debris generation during later processing steps.
Solution Approach 2:
The patent introduces dielectric and passivation layers as intermediary protective structures that are formed after dicing. These layers act as mediators that cover the diced surfaces, preventing direct exposure to contaminants and reducing debris generation during subsequent handling and processing operations.
3Shape
If alternating stack is removed to form trench, then the trench structure is created, but additional process steps are required
Solution Approach 1:
The patent extracts or removes the alternating stack material in specific regions to form trench structures. This extraction process creates the desired trench geometry while the remaining alternating stacks in other regions provide the necessary electrical connections, achieving both trench formation and functional integrity.
Solution Approach 2:
The patent applies local quality by selectively removing alternating stacks only in regions where trenches are needed, while preserving the alternating stack structure in regions where electrical connections are required. This localized modification achieves the trench shape without unnecessarily complicating the entire device structure.
Data Source
AI summary
A method for fabricating a semiconductor device includes the steps of defining a scribe line on a front side of a wafer, forming an inter-metal dielectric (IMD) layer on the wafer, forming an alternating stack on the IMD layer, removing the alternating stack to form a trench, forming a passivation layer extending from the alternating stack to the trench, and then performing a dicing process along the scribe line to dice the passivation layer and the wafer.