Wafer-Level Passive Integration for Compact IC Voltage Regulation
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Solution Overview
Problem
Current methods for integrating voltage regulation components on integrated circuit dies face challenges such as complex processes, high yield loss, increased cost, and limited specifications due to formation during CMOS processing, and inefficient space usage and electrical losses with discrete components on-package.
Innovation Solution
A semiconductor device design where passive devices like inductors and capacitors are integrated on separate substrates coupled to the integrated circuit using metallization, with insulating material filling gaps and pillars providing direct input/output connections, allowing for efficient voltage regulation without the limitations of CMOS processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If inductors and capacitors are formed during CMOS processing, then voltage regulation components are integrated on the die, but the process becomes complex with high yield loss and increased cost
Solution Approach 1:
The patent segments the voltage regulation components (inductors and capacitors) from the integrated circuit die by forming them on a separate substrate. This segmentation allows the IC to be manufactured using standard CMOS processes without the complexity of forming passive devices, while the passive devices are fabricated separately on a different substrate using appropriate processes, thereby reducing overall process complexity and yield loss.
Solution Approach 2:
The patent introduces an intermediary substrate that carries both the integrated circuit and the passive devices. This intermediary substrate acts as a mediator that couples the IC die to the passive devices through controlled impedance traces, eliminating the need to form passive devices directly during CMOS processing while maintaining electrical connectivity.
2Adaptability or versatility
If inductors and capacitors are formed during CMOS processing, then voltage regulation is integrated, but specifications are limited by CMOS process parameters
Solution Approach 1:
By segmenting the passive devices from the CMOS IC manufacturing process and forming them on a separate substrate, the patent enables the use of different fabrication processes optimized for specific passive device specifications. This allows for greater adaptability in terms of inductor Q-factor, capacitor ESL, and other parameters without being constrained by CMOS process limitations.
3Loss of energy
If discrete inductors and capacitors are provided on-package, then voltage regulation components are included, but large real estate space is required and electrical losses increase
Solution Approach 1:
The patent merges the integrated circuit die with the passive devices on a common substrate, creating a unified structure where the IC and passive components are closely integrated. This merging reduces the overall package footprint compared to discrete on-package components while minimizing electrical losses through optimized interconnections and controlled impedance traces.
Solution Approach 2:
The patent utilizes three-dimensional integration by stacking the IC die and passive devices in different layers on the substrate, with vertical interconnections through vias. This dimensional approach reduces the planar footprint while maintaining electrical performance, effectively reducing both package space and electrical losses.
Data Source
AI summary
A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate. Interconnects in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization.