Semiconductor Wafer Patterning for Precise Chip Position Identification
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Solution Overview
Problem
Existing methods face challenges in accurately identifying the position of semiconductor chips within a wafer, particularly when grinding marks are similar, making it difficult to distinguish between chips.
Innovation Solution
A method involving the formation of unique patterns on semiconductor chips using a combination of first and second repeating patterns, along with grinding marks on the backside of the wafer, allows for precise identification of chip positions without the need for image processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single repeating pattern is used to form unique patterns on semiconductor chips, then the manufacturing process is simple, but it becomes difficult to identify chip positions when grinding marks are similar
Solution Approach 1:
The patent divides the unique pattern formation into two separate repeating patterns (first and second repeating patterns) instead of using a single pattern. Each chip receives patterns from both repeating patterns, creating a composite unique pattern that combines features from both. This segmentation allows for more distinctive identification while maintaining manufacturing simplicity through the use of standard photolithography processes.
Solution Approach 2:
The patent introduces asymmetry by using two different repeating patterns with distinct characteristics rather than repeating the same pattern. The combination of these asymmetric patterns creates unique composite patterns for each chip position, enabling accurate identification even when grinding marks are similar. The asymmetric design ensures that no two chips have identical pattern combinations.
2Measurement precision
If image processing is used to identify chip positions based on grinding marks, then position identification can be performed, but costs increase due to the need for image processing equipment and analysis
Solution Approach 1:
The patent makes the semiconductor chips self-identifying by forming unique patterns directly on each chip during the photolithography process. These patterns serve as built-in identification markers that can be recognized without external image processing equipment. The chips essentially identify themselves through their unique pattern combinations, eliminating the need for complex imaging and analysis systems.
Solution Approach 2:
The patent extracts the identification function from the grinding marks and embeds it directly into the chip patterns through photolithography. Instead of relying on external image processing to analyze grinding marks, the identification information is taken out and integrated into the chip structure itself as unique patterns, simplifying the identification process.
3Device complexity
If grinding marks are used for position identification, then no additional patterns are needed on the chip, but similar grinding marks make it difficult to distinguish between chips
Solution Approach 1:
The patent merges the grinding mark identification method with photolithography pattern formation. Each chip receives unique patterns from two repeating patterns during photolithography, and these patterns are combined with the grinding marks to create a comprehensive identification system. The combination of pattern features from both repeating patterns provides sufficient distinction capability without adding excessive complexity to individual chip patterns.
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming semiconductor devices from a semiconductor wafer and identifying a position of the semiconductor device in the semiconductor wafer, wherein the forming the semiconductor devices includes forming a first repeating pattern including i semiconductor devices each having a unique pattern, forming a second repeating pattern including j semiconductor devices each having a unique pattern, defining semiconductor devices on the semiconductor wafer such that each of the k semiconductor devices has a unique pattern based on the first and second repeating patterns, and grinding a backside of the semiconductor wafer, wherein each unique pattern of the k semiconductor devices is composed of a combination of the unique patterns of the first and second repeating patterns, wherein the position of the semiconductor device is identified based on the unique patterns of the first and second repeating patterns and an angle of a grinding mark.