Wafer Patterning via Self-Aligned Spacer Double Patterning
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Solution Overview
Problem
As semiconductor technologies advance to feature sizes below 14 nanometers, existing lithographic techniques face challenges in achieving fine pitch reduction and maintaining line edge and width roughness, necessitating innovative patterning methods beyond conventional optical limitations.
Innovation Solution
A method involving double patterning techniques, including self-aligned spacer double patterning, where a substrate with a first relief pattern is etched and filled with materials to form bi-layer mandrels, followed by sidewall spacer formation and planarization, resulting in a multi-line layer with improved line edge and width roughness and square profile lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic techniques are used, then manufacturing simplicity is maintained, but pitch reduction capability and feature size below 14 nanometers cannot be achieved
Solution Approach 1:
The patterning process is divided into multiple discrete steps: forming initial mandrels, depositing first spacer material, removing mandrels, depositing second spacer material, and selective removal. This segmentation allows each step to be optimized independently, achieving pitch reduction below 14nm while maintaining process control and quality
Solution Approach 2:
Mandrel structures are formed in advance as templates before the actual pattern transfer. These preliminary mandrels guide the subsequent spacer deposition and pattern formation, enabling precise pitch control. The mandrels are removed after serving their templating function, leaving the desired fine-pitch pattern
2Manufacturing precision
If pitch reduction techniques are applied, then feature size below 14 nanometers is achieved, but line edge roughness and width roughness increase
Solution Approach 1:
The spacer structures are self-aligned to the mandrels through conformal deposition, automatically forming with precise dimensional control. This self-aligned mechanism eliminates alignment errors and reduces line edge roughness. The spacer width is determined by deposition thickness rather than lithographic patterning, providing better dimensional control and reduced width roughness
Solution Approach 2:
The patent replaces lithographic pattern transfer with a deposition-based spacer formation mechanism. Instead of using light exposure and chemical development that introduce roughness, the process uses physical vapor deposition or chemical vapor deposition to form spacers with atomic-layer precision, significantly reducing line edge and width roughness
3Manufacturing precision
If multiple patterning steps are used, then pitch reduction is achieved, but manufacturing productivity decreases
Solution Approach 1:
Multiple patterning operations are merged into a single integrated process flow on the same wafer. The first and second spacer materials are deposited and patterned in sequence without wafer re-entry, combining what would traditionally require multiple separate lithography steps into one continuous manufacturing cycle, thereby maintaining higher productivity
Solution Approach 2:
The process transitions from planar 2D patterning to 3D multi-layer spacer formation, then uses selective removal to achieve the final pattern. This dimensional approach allows pitch multiplication while maintaining manufacturing efficiency by utilizing vertical layering rather than sequential lateral patterning steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of patterns with reduced pitch and improved line edge and width roughness, suitable for feature sizes below 12 nanometers, extending the capabilities of photolithography and enhancing microfabrication processes.
Implementation Method 1
An etch operation selectively etches the layer of photoresist only resulting in the layer of photoresist being laterally etched from an initial width of lines to a resulting width of lines equal to three fifths of an initial width of lines of photoresist
Implementation Method 2
A fill material fills spaces between structures of the first relief pattern, covers horizontal top surfaces of the anti-reflective coating layer, and leaves top surfaces of the layer of photoresist uncovered
Implementation Method 3
A second etch operation is executed that removes the layer of photoresist and anisotropically etches uncovered portions of the anti-reflective coating layer and the third layer
Implementation Method 4
The pattern defined by remaining portions of the third layer is transferred into a fourth layer and into a fifth layer, using the third layer and second layer as an etch mask
Implementation Method 5
The substrate is then planarized by removing the fourth layer and removing material from the sidewall spacers and the second fill material down to a top surface of the fifth layer such that a multi-line layer is formed having a planar surface at the top surface of the fifth layer
Data Source
AI summary
Techniques herein include a method of patterning semiconductor wafers with improved line edge roughness (LER) and/or line width roughness (LWR), including lines below 12 nm in width. An initial bilayer mandrel is formed. The top layer is trimmed to a particular ratio. A reversal material protects uncovered portions of the lower layer, while a central portion is removed, resulting in two mandrels, each one fifth the initial mandrel width. The resulting mandrels are transferred into two underlying layers to form second bilayer mandrels. Sidewall spacers are formed on the second bilayer mandrels, and a fill material can fill remaining spaces. A planarization step can planarize the substrate to a bottom layer of the second bilayer mandrels, which results in a multi-line layer having square profile lines at 1:1 spacing ratio without spacer rounding.