Semiconductor Wafer Planarization via Dual-Layer Spin Coating
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Solution Overview
Problem
The increasing integration of semiconductor devices requires advanced planarization techniques to form fine patterns and multi-layered wirings, but existing chemical mechanical polishing (CMP) processes often introduce defects and are less effective at planarizing the edge regions of wafers.
Innovation Solution
A method involving the formation of a first material layer with a protrusion at the edge of the semiconductor wafer, followed by a second material layer that fills the receiving space defined by the protrusion, providing a planar surface without the need for a separate CMP process, using materials with different properties and solvents to ensure effective interlayer gap-fill and adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is used for planarization, then surface flatness is improved, but defects and particles are created on the wafer surface
Solution Approach 1:
The invention extracts and removes the problematic CMP process from the manufacturing flow, replacing it with a spin-coating based planarization method using two different materials that self-planarize without causing defects or particles on the wafer surface
Solution Approach 2:
The invention changes the fundamental parameter of the planarization approach by using materials with different properties (first material layer and second material layer with different solvents) that self-adjust during spin-coating to achieve flatness without mechanical polishing
2Manufacturing precision
If CMP process is used for planarization, then wafer surface is flattened, but edge regions remain vulnerable to planarization
Solution Approach 1:
The invention applies local quality by using two different materials with different properties in different regions of the wafer - the first material layer covers the entire surface while the second material layer is applied selectively to achieve uniform planarization across both center and edge regions
3Manufacturing precision
If multiple material layers are formed with different properties, then complete planarization is achieved, but process complexity increases
Solution Approach 1:
The invention merges the planarization function into the existing spin-coating process by forming two material layers with different properties that self-planarize during the coating process, eliminating the need for a separate CMP process step
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables complete planarization of semiconductor wafers, reducing defects and eliminating the need for CMP, while being applicable to both non-planar and warped surfaces, enhancing the manufacturing process for semiconductor integrated circuit devices.
Implementation Method 1
A second material layer may be formed on the first material layer... providing a planar surface of the semiconductor wafer
Data Source
AI summary
A semiconductor integrated circuit device and a method of manufacturing the same are disclosed. A semiconductor wafer having a surface step is prepared. A first material layer is formed on an upper surface of the semiconductor wafer so that a protrusion is formed in a portion thereof corresponding to an edge region of the semiconductor wafer. A second material layer is formed on the first material layer.