Wafer Planarization via Etching-Resist Layer for LCOS Mirror Flatness

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Solution Overview

Problem

Conventional Chemical Mechanical Polishing (CMP) methods fail to achieve the required surface flatness for advanced semiconductor applications, particularly in Liquid Crystal on Silicon (LCOS) technology, resulting in concentric ring recesses on the top metal layer that degrade its quality and prevent it from being used as a mirror.

Innovation Solution

A method involving the formation of an etching-resist layer with a greater thickness in recesses than outside, followed by selective etching to ensure the wafer surface is flush or lower than the recess bottom, avoiding the CMP process and its associated surface defects, and using dry etching to expose the top metal layer completely.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional CMP process is used for planarization, then the manufacturing process is simple and fast, but the wafer surface flatness is insufficient and concentric ring recesses are formed

Engineering Contradiction:

Improvewafer surface flatnessVSAvoidprocess complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

An etching-resist layer is formed in advance to fill the recesses on the wafer surface before the planarization process. This preliminary action creates a compensated surface that allows subsequent etching to achieve the required flatness without the defects caused by conventional CMP

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent replaces the mechanical CMP process with a chemical etching process. Instead of mechanically polishing the surface, the invention uses selective etching of the etching-resist layer and wafer surface to achieve planarization, thereby eliminating the concentric ring recesses caused by mechanical polishing

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Manufacturing precision

If CMP process is used to polish the insulating oxide layer, then the trench is filled and surface is smoothed, but concentric ring recesses are transferred to the top metal layer

Engineering Contradiction:

Improvesurface flatness of top metal layerVSAvoidconcentric ring recesses

Core Design Contradiction:

Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent replaces the mechanical CMP polishing step with a chemical etching process. The etching-resist layer is selectively etched along with the insulating oxide layer, and since the etching-resist layer fills the recesses, the resulting surface does not have the concentric ring recesses that would be transferred to the top metal layer

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The etching-resist layer serves as an intermediary substance that fills the recesses and protects them during the etching process. This intermediary layer ensures that the recesses are not etched and do not transfer to the final metal layer surface

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures a high-quality, flat top metal layer, improving the display quality of LCOS LCDs by eliminating concentric ring recesses and maintaining wafer surface flatness, suitable for precise optical applications.

Implementation Method 1

forming an etching-resist layer on the surface layer to fill the recess

Methodology Applied

Scientific EffectSpin coating: Spin Coating

Implementation Method 2

etching the etching-resist layer and the surface layer; wherein, an etching speed of the surface layer is higher than that of the etching-resist layer

Methodology Applied

Scientific EffectEtching:

Implementation Method 3

the entire insulating oxide layer on the top metal layer 40 is removed by a dry etching process

Methodology Applied

Scientific EffectDry etching:

Data Source

PatentUS8058175B2Method for planarization of wafer and method for formation of isolation structure in top metal layer

Publication Date: 2011.11.15 SEMICON MFG INT (SHANGHAI) CORP

AI summary

The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower than the bottom of the recess, the etching speed of the surface layer being higher than that of the etching-resist layer; removing the etching-resist layer; and etching the surface layer to a predetermined depth. The method can avoid concentric ring recesses on the surface of the wafer resulted from a chemical mechanical polishing (CMP) process in the prior art, and can be used to obtain a wafer surface suitable for optical applications.