Wafer Planarization for Image Sensors via CMP
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Solution Overview
Problem
In wafer-to-wafer bonding for image sensors, the difference in surface characteristics between chip and scribe lane regions leads to steps during chemical mechanical polishing (CMP), affecting bonding strength and reliability.
Innovation Solution
A method involving the formation of specific through-holes and pad metal layers in both regions, followed by CMP to expose the insulating layer surfaces uniformly, ensuring flat bonding surfaces and preventing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing (CMP) is performed on the wafer surface to planarize the bonding surface, then the bonding surface should be entirely flat to secure bonding strength, but steps are formed between the chip region and the scribe lane region due to different surface characteristics
Solution Approach 1:
The patent applies different polishing conditions to different regions of the wafer. Specifically, the chip region and scribe lane region are polished with different pressures, speeds, or slurry flow rates to account for their different surface characteristics. This local differentiation allows each region to achieve optimal flatness without creating steps at the boundary, thereby resolving the contradiction between overall flatness and regional uniformity.
Solution Approach 2:
The patent changes polishing parameters (such as pressure, speed, slurry composition, or temperature) during the CMP process to adapt to the different surface characteristics of the chip region and scribe lane region. By dynamically adjusting these parameters, the polishing rate and surface quality are optimized for each region, preventing step formation while maintaining overall flatness and bonding reliability.
2Ease of manufacture
If the chip region and scribe lane region are polished uniformly, then the processing is simple, but steps are formed due to different surface characteristics affecting bonding quality
Solution Approach 1:
The patent implements local quality control by applying region-specific polishing conditions to the chip region and scribe lane region. This may involve using different polishing pads, adjusting pressure distribution, or controlling slurry flow differently for each region. While this increases process complexity compared to uniform polishing, it achieves the necessary flatness and eliminates steps that would compromise bonding quality.
Solution Approach 2:
The patent segments the wafer surface into distinct regions (chip region and scribe lane region) and applies independent polishing control to each segment. This segmentation allows for customized polishing parameters in each region, achieving superior flatness and step-free boundaries, though it requires more complex process control compared to uniform polishing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the bonding characteristics and reliability of image sensors by maintaining a flat surface across chip and scribe lane regions, preventing voids and improving contact between conductive pads.
Implementation Method 1
polishing the polishing layer and the pad metal layer by a chemical mechanical polishing (CMP) process
Data Source
AI summary
A method for wafer planarization includes forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe lane region; forming a first through-hole in the polishing layer in the chip region and the scribe lane region and a second through-hole in the second insulating layer in the chip region, wherein the second through-hole and the first through-hole meet in the chip region; forming a pad metal layer inside the first through-hole and the second through-hole and on an upper surface of the polishing layer; and polishing the polishing layer and the pad metal layer by a chemical mechanical polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe lane region.