Wafer Plasma Dicing Sequence for Low-Damage Chip Separation
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Solution Overview
Problem
Current methods for producing display devices for augmented reality (AR) and virtual reality (VR) applications face challenges due to the use of long wires or metal interconnections, which consume space and complicate mounting, especially in larger scale products.
Innovation Solution
A method involving plasma dicing, laminating, grinding, and expanding processes to dice a wafer into chips, with distinct sidewall profiles and different material compositions for bonding pads, allowing for efficient integration of display modules and external circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If long wires or metal interconnections are used to connect DDICs to display modules, then the connection is established, but space consumption increases and mounting difficulty increases
Solution Approach 1:
The invention segments the wafer into multiple chips using plasma dicing to create scribe lines, allowing individual chips to be processed and mounted separately. This eliminates the need for long interconnections between DDICs and display modules by integrating them into a single chip structure, thereby reducing space consumption and simplifying mounting operations.
Solution Approach 2:
The invention introduces a vertical dimension by forming recesses and stacking components in three-dimensional space. Display modules and DDICs are positioned at different heights and connected through vertical vias and conductive structures, eliminating the need for long horizontal wire connections and reducing the overall footprint of the device.
2Productivity
If plasma dicing process is used to dice the wafer, then chip yield increases and edge damage is minimized, but the process complexity increases
Solution Approach 1:
The invention replaces traditional mechanical dicing methods with a plasma-based dicing process. Plasma etching is used to create scribe lines by removing material chemically rather than mechanically cutting the wafer. This substitution eliminates mechanical stress and physical contact that cause edge damage, while enabling precise patterning and higher chip yields through controlled material removal.
3Ease of manufacture
If the wafer is diced completely into separate chips, then individual chip processing is enabled, but chip edge damage increases and yield decreases
Solution Approach 1:
The invention performs preliminary plasma dicing to create scribe lines that define chip boundaries but do not completely separate the chips. The wafer is partially diced while still maintaining structural integrity, allowing subsequent processing steps to be performed on the wafer level. Individual chip processing is then enabled when needed, while minimizing edge damage by avoiding complete mechanical separation until the final stage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces space consumption and simplifies mounting by minimizing damage to chip edges and increasing chip yield, while maintaining consistent chip and wafer sizes.
Implementation Method 1
performing a plasma dicing process to dice the wafer along the scribe line without separating the wafer completely
Implementation Method 2
performing an expanding process to divide the wafer into chips
Data Source
AI summary
A method for fabricating a semiconductor device includes the steps of first providing a wafer, forming a scribe line on a front side of the wafer, performing a plasma dicing process to dice the wafer along the scribe line without separating the wafer completely, performing a laminating process to form a tape on the front side of the wafer, performing a grinding process on a backside of the wafer, and then performing an expanding process to divide the wafer into chips.