Semiconductor Wafer Plating Bus Using Last Interconnect Layer

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Solution Overview

Problem

Current semiconductor processing methods for forming wirebond pads using electrolytic plating are costly due to the need for a plating bus layer that must be applied and removed, while electroless plating is harder to control and results in reduced yield.

Innovation Solution

The last interconnect metal layer is used to form the plating bus during semiconductor wafer fabrication, which is severed and discarded during die singulation, eliminating the need for a plating bus over the final passivation layer and reducing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a plating bus layer is applied over the final passivation layer for electrolytic plating, then the electrolytic plating process can be performed, but additional cost processes are added for applying and removing the plating bus

Engineering Contradiction:
Improvecontrol over plating processVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The last metal interconnect layer is designed to serve dual purposes: as the functional interconnect layer for the semiconductor device and as the plating bus for electrolytic plating. This multi-functionality eliminates the need for a separate plating bus layer, reducing manufacturing steps and costs while maintaining electrolytic plating control

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention merges the interconnect layer and plating bus into a single structure. The last metal interconnect layer is extended to form the plating bus, combining two previously separate components into one, thereby eliminating the need for separate application and removal processes

Inventive Principle:
Principle #5Merging (Combining)

2Ease of manufacture

If electroless plating is used instead of electrolytic plating to avoid plating bus, then manufacturing cost is reduced, but the process is harder to control and results in reduced yield

Engineering Contradiction:
Improvemanufacturing costVSAvoidprocess control and yield
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

By making the last metal interconnect layer serve as both the functional interconnect and the plating bus, the invention enables electrolytic plating without requiring a separate plating bus structure, thus avoiding the control issues of electroless plating while eliminating the extra cost of plating bus application and removal

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention extracts the plating bus function from a separate layer and integrates it into the existing last metal interconnect layer, thereby eliminating the need for separate plating bus processing steps that add cost

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If a separate plating bus layer is used over the final passivation layer, then electrolytic plating can be performed, but the plating bus must be removed after plating adding to process complexity

Engineering Contradiction:
Improveplating process controlVSAvoidnumber of process steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention combines the interconnect layer and plating bus into a single structure, eliminating the need for separate application and removal steps for the plating bus, thereby reducing process complexity while maintaining electrolytic plating capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The last metal interconnect layer serves dual functions as both the functional interconnect and the plating bus, eliminating the need for a separate plating bus layer and its associated process steps

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces costs by eliminating the need for additional plating bus application and removal steps while maintaining control over the electrolytic plating process, improving yield compared to electroless plating.

Implementation Method 1

Plating may be performed using either an electroless plating process or an electrolytic plating process

Methodology Applied
Scientific EffectElectrolytic plating: Electroplating

Data Source

PatentUS8895409B2Semiconductor wafer plating bus and method for forming
Publication Date: 2014.11.25 NXP USA INC
  • US8895409B2 patent drawing
  • US8895409B2 patent drawing
  • US8895409B2 patent drawing

AI summary

A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal.