Wafer Plating Structure for UBM and Redistribution Layers
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Solution Overview
Problem
Conventional semiconductor package manufacturing processes for wafer level packages are inefficient, requiring numerous sputtering, patterning, exposure, and etching processes, leading to increased manufacturing time and cost due to the complexity of forming under-bump-metal (UBM) and redistribution layers.
Innovation Solution
A plating structure that extends from the bonding pad to the sawing line of the wafer during the redistribution layer plating process, reducing the need for multiple sputtering and etching steps by simultaneously forming UBM and redistribution layers, and using a plating device with a plating connection line and bar to integrate the UBM formation with the redistribution layer process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional sputtering and patterning processes are used to form UBM and redistribution layers, then manufacturing precision is maintained, but manufacturing time and process complexity increase
Solution Approach 1:
The patent combines the UBM formation process with the redistribution layer formation process into a single plating operation. The plating structure extends from the bonding pad through the chip to the sawing line, allowing simultaneous deposition of metal layers for both UBM and redistribution functions, thereby reducing manufacturing time while maintaining precision through integrated process control
Solution Approach 2:
The plating structure serves multiple functions: it forms the UBM on the bonding pad, creates the redistribution layer extending to the sawing line, and provides electrical connectivity throughout. This multi-functional approach eliminates the need for separate sputtering and patterning steps, reducing process time while maintaining manufacturing precision through unified plating parameters
2Manufacturing precision
If multiple sputtering, patterning, exposure, and etching processes are used, then UBM and redistribution layers are formed with required precision, but device complexity increases
Solution Approach 1:
The patent merges multiple discrete processes (sputtering, patterning, exposure, etching) into a single plating process. The plating structure is designed to extend continuously from the bonding pad through the chip to the sawing line, allowing all layer formations to occur simultaneously through one deposition step, thereby reducing device complexity while maintaining precision
Solution Approach 2:
The patent extracts and eliminates unnecessary intermediate processes from the conventional manufacturing flow. By using plating directly to form both UBM and redistribution layers without separate sputtering and patterning steps, the process complexity is reduced while the required manufacturing precision is achieved through controlled plating parameters
3Manufacturing precision
If separate processes are used for UBM formation and redistribution layer formation, then each layer can be optimized independently, but manufacturing cost increases
Solution Approach 1:
The patent combines UBM formation and redistribution layer formation into a single plating process, reducing manufacturing cost through process integration. The plating structure extends continuously to allow both layers to be formed in one step, eliminating the need for multiple equipment setups and process optimizations while maintaining the ability to control layer properties through plating parameters
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of manufacturing processes and time required, lowering the overall cost and complexity of producing wafer level packages by integrating UBM and redistribution layer formation, thereby enhancing efficiency.
Implementation Method 1
a plating structure for forming an under bump metal on redistribution layers on the plurality of semiconductor die
Data Source
AI summary
A plating structure for wafer level packages are disclosed and may include a semiconductor wafer comprising a plurality of semiconductor die and a plating structure for forming an under bump metal on redistribution layers on the plurality of semiconductor die. The plating structure may comprise a plating connection line around a periphery of the semiconductor wafer, and a plating bar coupling the plating connection line to plating traces on the plurality of semiconductor die. The plating traces may be electrically coupled to the redistribution layers on the plurality of semiconductor die. The semiconductor wafer may comprise a reconstituted wafer of said semiconductor die. The semiconductor wafer may comprise a wafer prior to singulating the plurality of semiconductor die. The plating bar may be located in a sawing line for the singulating of the plurality of semiconductor die. A passivation layer may cover the redistribution layer and the plating traces.