Double-Side Polishing Wafer Flatness ERO Control
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Solution Overview
Problem
Semiconductor wafers exhibit edge roll-off (ERO) during polishing with double-side polishing machines, leading to wastage of edge regions that do not meet flatness standards, and existing methods struggle to improve ERO while maintaining high flatness.
Innovation Solution
Implementing a new evaluation standard that includes ERO, along with GBIR and SFQR, and using a double-side polishing machine with multiple polishing steps, where the wafer thickness is set to be larger than the carrier by 5-10 μm initially and polished to match the carrier thickness, with specific polishing conditions to achieve reduced ERO and high flatness across the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a semiconductor wafer is polished with a double-side polishing machine, then the front and back surfaces can be simultaneously polished to achieve high flatness, but edge roll-off (ERO) occurs at the edge region due to pressure difference between central and edge regions, causing wasteful discarding of edge portions
Solution Approach 1:
The patent applies local quality by implementing multi-stage polishing with differently configured press platens. The first press platen has a larger diameter than the second press platen, creating different pressure distributions on the wafer surface during each polishing stage. This allows the central region to be polished with higher pressure initially, then the edge region to receive focused attention in subsequent stages, thereby reducing ERO while maintaining overall flatness and preserving edge regions.
Solution Approach 2:
The patent segments the polishing process into multiple stages with different press platen configurations. Instead of using a single uniform polishing approach, the process divides the wafer treatment into sequential steps where each stage addresses specific regions or aspects of the wafer surface, allowing optimized control over both central and edge region flatness.
2Manufacturing precision
If the thickness of the semiconductor wafer is set larger than the carrier by 5 μm to 10 μm prior to final polishing and polished to match the carrier thickness, then the allowance is reduced to 0 μm to 5 μm, but maintaining high flatness while reducing ERO requires precise control of polishing conditions
Solution Approach 1:
The patent applies parameter changes by systematically varying polishing conditions across multiple stages. The press platens are configured with different diameters and applied pressures for each polishing stage. The first press platen has a larger diameter and different pressure characteristics than the second press platen, allowing optimization of material removal rates and pressure distribution at each stage to achieve the target thickness tolerance while controlling ERO.
Solution Approach 2:
The patent applies preliminary action by performing initial polishing stages that remove excess material and prepare the wafer surface before the final polishing stage. The first press platen performs preliminary polishing with less stringent precision requirements, removing the bulk of the 5-10 μm thickness difference, while the second press platen performs the final precision polishing to achieve the 0-5 μm allowance and target flatness, thereby simplifying the overall process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the utilization of edge regions while maintaining high flatness, reducing ERO to 0.2 μm or less and achieving optimal GBIR, SBIR, and SFQR values, thereby improving the overall quality and reducing wastage.
Implementation Method 1
front and back surfaces of the semiconductor wafers are simultaneously polished with a double-side polishing machine
Data Source
AI summary
In a method of manufacturing semiconductor wafers, front and back surfaces of the semiconductor wafers are simultaneously polished with a double-side polishing machine that includes: a carrier for accommodating the semiconductor wafer; and an upper press platen and a lower press platen for sandwiching the carrier. The method includes: accommodating the semiconductor wafer in the carrier while a thickness of the semiconductor wafer is set to be larger than a thickness of the carrier by 0 μm to 5 μm; and polishing the semiconductor wafer while feeding a polishing slurry to between the surfaces of the semiconductor wafer and surfaces of the press platens. In the polishing, an allowance of both surfaces of the semiconductor wafer is set at 5 μm or less in total.