Semiconductor Wafer Probe Testing via Film Frame Openings

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Solution Overview

Problem

Semiconductor wafers, especially thin and warped ones, face challenges during testing due to breakage risks from probe pressure and incomplete feature sets, leading to reduced quality assurance and increased manufacturing costs, as current testing methods struggle to effectively contact and inspect all features before wafer thinning.

Innovation Solution

A method involving the thinning of semiconductor wafers using an edge support ring and subsequent probe testing from the backside through openings in a film frame, allowing for stable and complete feature set testing post-thinning, with conductive channels enabling direct electrical contact and inspection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wafer testing is performed before wafer thinning, then testing can be conducted on larger wafers, but the test is incomplete because certain features are not present and probe pressure causes breakage or damage

Engineering Contradiction:
Improvequality assuranceVSAvoidprobe pressure damage
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies preliminary action by performing wafer thinning before testing, so that the wafer is prepared in advance with the correct thickness and all features are present. This allows testing to be conducted on the thinned wafer with complete feature set, avoiding the damage caused by probing thick wafers before thinning.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If wafer testing is performed before wafer thinning, then testing can be conducted earlier in the process, but the test is incomplete because certain features added post-wafer thinning are not present

Engineering Contradiction:
Improvetesting timingVSAvoidquality assurance
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent performs wafer thinning as a preliminary action before testing, ensuring that all features including back-side metal are present before the testing stage. This sequencing guarantees complete quality assurance while maintaining efficient process timing.

Inventive Principle:
Principle #10Preliminary action

3Volume of moving object

If wafer thickness is reduced to minimize package size, then the semiconductor package size is minimized, but the wafer becomes susceptible to warpage and breakage during testing

Engineering Contradiction:
Improvepackage sizeVSAvoidwafer strength
Core Design Contradiction:
Volume of moving objectVSStrength

Solution Approach 1:

The patent applies preliminary action by performing wafer thinning before testing, so that the wafer is reduced to its final thin dimensions before the testing stage. This ensures that testing is conducted on the thinned wafer with appropriate structural integrity, avoiding the weaknesses inherent in testing thick wafers that would require excessive thinning later.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10461000B2Semiconductor wafer and method of probe testing
Publication Date: 2019.10.29 SEMICON COMPONENTS IND LLC
  • US10461000B2 patent drawing
  • US10461000B2 patent drawing
  • US10461000B2 patent drawing

AI summary

A semiconductor test system has a wafer holder with a tape portion and one or more openings through the tape portion. A semiconductor wafer is mounted over the opening in the tape portion of the wafer holder with an electrical connection to the semiconductor wafer through the opening in the tape portion during probe test. A plurality of bumps can be formed on the semiconductor wafer. The semiconductor wafer can be a stacked semiconductor wafer. A conductive trace can be formed on the tape portion and the semiconductor wafer probe tested through the conductive trace. An active surface or non-active surface of the semiconductor wafer can be oriented toward the tape portion. The electrical connection to the semiconductor wafer through the opening in the tape portion can be a ground reference node. A conductive layer is formed over a non-active surface of the semiconductor wafer.