Wafer Processing Using Reused Photolithographic Masks
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Solution Overview
Problem
The demand for thinner silicon interposers to accommodate miniaturized electronic devices with fine pitch arrays of integrated circuits necessitates the development of methods for producing silicon interposers with multiple wiring layers, as existing epoxy resin interposers are too thick and require additional carriers for integration.
Innovation Solution
A method of processing wafers to form interposers involves establishing a line of symmetry on both sides of the wafer to define adjacent die areas, using photolithographic masks to create multiple interconnection layers, and forming electrically conductive vias, allowing for the reuse of masks and ensuring thermal stability through common semiconductor materials like silicon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If epoxy resin substrate is used for interposer construction, then ease of manufacture is improved, but the thickness of the interposer increases which is not desirable for miniaturized devices
Solution Approach 1:
The invention changes the material parameter from epoxy resin to silicon substrate, which fundamentally alters the thickness characteristic while maintaining manufacturability through established semiconductor processing techniques
2Adaptability or versatility
If multiple wiring layers are added to accommodate fine pitch arrays, then adaptability is improved, but device complexity increases
Solution Approach 1:
The invention segments the wafer into multiple die areas with independent wiring layer configurations, allowing each segment to be optimized for specific fine pitch array requirements while managing overall complexity through modular design
Solution Approach 2:
The invention adds multiple wiring layers in the vertical dimension to accommodate fine pitch arrays, transforming a two-dimensional layout problem into a three-dimensional structure that provides additional routing capacity
3Ease of manufacture
If photolithographic masks are reused for forming multiple interconnection layers, then manufacturing cost is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The invention establishes a line of symmetry and pre-defines die area configurations before mask application, allowing the same mask to be reused across multiple layers with consistent alignment references that maintain precision requirements
Data Source
AI summary
A method of processing a wafer includes establishing a fine of symmetry defining left and right die areas on a front side of the wafer and left and right die areas on a back side. A first mask is used to form a first interconnection layer on the left and right die areas comprising a first portion on the left die area and second portion different than the first portion on the right die area. A second mask is used to form a second interconnection layer on the left and right die areas comprising a third portion on the left die area and fourth portion different than the third portion on the right die area. The first mask is reused to form a third interconnection layer on the left and right die areas on a back side, and the second mask to form a fourth interconnection layer on the left and right die areas on a back side.