Semiconductor Wafer Protective Coating for Flatness and Edge Drop
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Solution Overview
Problem
Semiconductor wafers face challenges in achieving uniform flatness and thickness due to irregularities in processing steps like epitaxial deposition, which result in issues such as quadruple symmetry and edge drop, especially during double-side polishing and chemical-mechanical polishing processes.
Innovation Solution
A method involving an etching step using hydrogen chloride or its mixture with hydrogen in an epitaxy reactor, followed by deposition, where one side of the wafer is coated with a protective layer to control material removal and deposition, specifically addressing edge region thickness fluctuations and quadruple symmetry by employing anti-quadruple symmetry etching techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If epitaxial deposition is performed on semiconductor wafers, then material is deposited on the wafer surface, but irregularities such as quadruple symmetry and edge drop occur due to different growth rates along crystal axes
Solution Approach 1:
The patent applies preliminary polishing (chemical-mechanical polishing or mechanical polishing) to the semiconductor wafer before epitaxial deposition to pre-compensate for expected thickness variations and quadruple symmetry irregularities. This preliminary action creates a more uniform base surface that reduces the impact of non-uniform deposition during the subsequent epitaxial growth process, thereby improving final surface flatness and thickness uniformity.
2Manufacturing precision
If double-side polishing is performed to improve flatness, then both sides of the wafer are processed simultaneously, but edge drop and thickness non-uniformity occur due to processing forces and guide device constraints
Solution Approach 1:
The patent applies different polishing pressures or conditions to different regions of the wafer during double-side polishing. By using local quality principles, the polishing process can be optimized for specific areas - for example, applying lighter pressure at the edges to prevent edge drop while maintaining appropriate pressure at the center for flatness control. This regional differentiation of polishing parameters helps resolve the contradiction between achieving overall flatness and maintaining edge geometry.
3Manufacturing precision
If coating processes are performed to deposit material on wafers, then epitaxial layers are formed, but uncontrolled material accumulates on reactor surfaces requiring periodic removal
Solution Approach 1:
The patent introduces a sacrificial coating or intermediary layer on the reactor surfaces that prevents uncontrolled material accumulation during epitaxial deposition. This intermediary layer acts as a mediator between the depositing material and the reactor walls, allowing for controlled material transfer and easier removal. Instead of material accumulating directly on reactor surfaces, it deposits on the sacrificial layer which can be periodically removed or regenerated, simplifying reactor maintenance while maintaining epitaxial layer quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of semiconductor wafers with significantly improved flatness and thickness uniformity, reducing quadruple symmetry and edge drop issues, and ensures better radial and circumferential thickness distribution.
Implementation Method 1
During the etching step, an etching gas consisting of hydrogen chloride or a mixture of hydrogen chloride and hydrogen is passed through the coating device
Implementation Method 2
a deposition gas is passed through the coating device to epitaxially deposit a layer on the semiconductor wafer
Data Source
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AI summary
The invention relates to a method for machining a semiconductor wafer (600). The semiconductor wafer (600) is arranged on a susceptor (310) in a coating device (300) and is then machined as part of a machining process. As part of the machining process, an etching gas is conducted through the coating device (300) in an etching step. The method is characterized in that a first semiconductor wafer (600) side (FS), which is subjected to a polishing process by means of CMP, or a second semiconductor wafer (600) side (BS), which lies opposite the first side, is coated with a protective layer (601) prior to the machining process.