Wafer Recognition Marks for Chip Package Position Tracking
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Solution Overview
Problem
In conventional chip packaging, it is challenging to maintain accurate fabrication conditions across the larger surface area of a wafer, particularly between central and peripheral regions, due to the need for adjusted process conditions, and there is a lack of relative position information for individual chip packages before dicing, which complicates identifying and addressing quality issues and improving yield.
Innovation Solution
A chip package is created with a substrate diced from a wafer, featuring a device region, conducting layers, an insulating layer, and a material layer with recognition marks that provide position information, allowing for precise identification of each chip package's original position within the wafer before dicing, facilitating adjusted fabrication conditions and easier troubleshooting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a wafer-level packaging process is adopted to reduce fabrication cost and time, then productivity is improved, but it becomes difficult to maintain accurate fabrication conditions across the larger surface area of the wafer, particularly between central and peripheral regions
Solution Approach 1:
The patent applies preliminary action by forming recognition marks on the wafer before the dicing process. These marks are created during the wafer-level packaging process, allowing position information to be recorded in advance. This enables subsequent identification of each chip package's original position without requiring additional steps after dicing, thus maintaining fabrication condition consistency across the larger wafer surface while preserving the productivity benefits of wafer-level processing.
2Productivity
If wafer-level packaging is used to simultaneously obtain multiple chip packages, then productivity is improved, but relative position information of individual chip packages is lost after dicing, making quality issue identification difficult
Solution Approach 1:
The recognition marks are formed on the wafer before dicing, recording the position information of each future chip package in advance. This preliminary recording ensures that even after the wafer is diced into individual chips, the position information remains intact and can be used to trace quality issues back to their original locations on the wafer, thus preventing information loss while maintaining batch processing productivity.
Solution Approach 2:
The patent creates a copy of position information by forming recognition marks that represent the spatial coordinates of each chip package on the wafer. These marks serve as informational copies that can be read after dicing to reconstruct the original position data, enabling quality tracking without requiring the physical wafer structure to remain intact.
3Manufacturing precision
If process conditions are adjusted for central and periphery portions of the wafer, then manufacturing precision is improved, but it requires relative position information that is not readily available in conventional wafer-level packaging
Solution Approach 1:
The recognition marks provide pre-recorded position information that simplifies process control. Instead of requiring complex real-time tracking systems to determine where each chip originated on the wafer, the position information is already encoded in the recognition marks formed during wafer processing. This reduces the complexity of position-specific process control while enabling precise adjustment of fabrication conditions for different wafer regions.
Data Source
AI summary
An embodiment of the invention provides a chip package which includes: a substrate, wherein the substrate is diced from a wafer; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a material layer formed on the insulating layer, wherein the material layer has a recognition mark, and the recognition mark shows position information of the substrate in the wafer before the substrate is diced from the wafer.