Semiconductor Wafer Relocation Wiring Pitch Reduction
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Solution Overview
Problem
The existing wafer process package technique for semiconductor devices faces challenges in reducing the pitch between electrode pads while ensuring reliability, as relocation wirings can cause damage to the insulating layers and lead to electrical characteristic issues due to stress and noise interference, and the use of organic insulating films can result in data loss during heat treatment.
Innovation Solution
A method is developed where a semiconductor wafer with inorganic and organic insulating layers is used, with the relocation wiring formed over the organic layer after heat treatment to prevent damage and data loss, and the width of the wiring is controlled to be equal to or smaller than the openings in the insulating members to maintain electrical integrity and reduce pitch between pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If relocation wiring is formed to reduce pitch between electrode pads, then device size is reduced, but damage to insulating layers and electrical characteristic issues occur due to stress and noise interference
Solution Approach 1:
The patent divides the insulating structure into multiple segments: a first insulating layer formed before relocation wiring, and a second insulating layer formed after relocation wiring. This segmentation allows the relocation wiring to be embedded in the first insulating layer while the second insulating layer provides additional protection, reducing stress and noise interference on the underlying layers and maintaining electrical characteristic stability while enabling pitch reduction.
Solution Approach 2:
The first insulating layer is formed preliminarily before forming the relocation wiring. This preliminary action provides a protective foundation that prevents damage to underlying structures during the relocation wiring formation process, allowing pitch reduction while maintaining reliability.
2Volume of moving object
If organic insulating film is used to reduce pitch, then device size is reduced, but data loss occurs during heat treatment
Solution Approach 1:
The patent uses a composite insulating structure combining an organic insulating film (first insulating layer) with an inorganic insulating film (second insulating layer). The organic layer enables pitch reduction while the inorganic layer provides thermal stability during heat treatment, preventing data loss. This composite approach allows the benefits of organic materials (flexibility, conformality) while mitigating their weaknesses (thermal sensitivity).
Solution Approach 2:
The second insulating layer is formed beforehand as a protective cushion over the first insulating layer before heat treatment. This beforehand cushioning protects the organic insulating film and underlying data structures from thermal damage during subsequent heat treatment processes, preventing data loss while maintaining the size-reduction benefits of the organic layer.
3Reliability
If multiple insulating layers are formed to protect relocation wiring, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct sequential steps: forming the first insulating layer, forming relocation wiring, and forming the second insulating layer. This segmentation allows each layer to be optimized independently and formed using standard semiconductor fabrication techniques, making the complex multi-layer structure manufacturable with existing process capabilities.
Solution Approach 2:
The first insulating layer serves multiple functions: it acts as an embedding medium for relocation wiring, provides initial protection during wiring formation, and serves as a base layer for the second insulating layer. This multi-functionality reduces the need for additional specialized layers, simplifying the overall manufacturing process while maintaining reliability.
Data Source
AI summary
Provided is a semiconductor device with improved reliability that achieves the reduction in size. A semiconductor wafer is provided that has a first insulating member with an opening that exposes from which an upper surface of an electrode pad. Subsequently, after forming a second insulating member over a main surface of the semiconductor wafer, another opening is formed to expose the upper surface of the electrode pad. Then, a probe needle is brought into contact with the electrode pad, to write data in a memory circuit at the main surface of the semiconductor wafer. After covering the upper surface of the electrode pad with a conductive cover film, a relocation wiring is formed. In the Y direction, the width of the relocation wiring positioned directly above the electrode pad is equal to or smaller than the width of the opening formed in the first insulating member.