Wafer Rework Determination Using Hotspot Simulation
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Solution Overview
Problem
Conventional methods for determining wafer rework in semiconductor manufacturing are inefficient due to reliance on worst-case critical dimension and overlay error tolerances, leading to increased manufacturing costs and resource utilization, without considering specific circuit designs or manufacturing condition variations.
Innovation Solution
The use of hotspot simulation to analyze metrology data from photoresist patterns, comparing actual data with simulated data to determine if rework is needed, based on process conditions such as focus, dose, and misalignment, allowing for design-specific and dynamic decision-making.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If worst-case critical dimension/overlay error tolerances are used for determining specifications, then manufacturing reliability is improved, but rework rates increase and manufacturing costs expand
Solution Approach 1:
The patent applies local quality by transitioning from uniform worst-case specifications across all wafers to localized, wafer-specific specifications based on actual manufacturing conditions. Each wafer receives customized tolerance thresholds derived from its specific process parameters (focus, dose, alignment), allowing precise quality control without unnecessary rework. This is implemented through the wafer evaluation module that compares individual wafer measurements against their specific simulated thresholds.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting specification thresholds based on actual manufacturing parameters (focus, dose, alignment) rather than using fixed worst-case values. The system simulates metrology data using specific process conditions for each wafer and derives customized tolerance levels, thereby optimizing the balance between reliability and rework rate through parameter-driven specification adaptation.
2Reliability
If worst-case critical dimension/overlay error tolerances are used for determining specifications, then manufacturing reliability is improved, but manufacturing costs increase
Solution Approach 1:
The patent applies local quality by transitioning from uniform worst-case specifications across all wafers to localized, wafer-specific specifications based on actual manufacturing conditions. Each wafer receives customized tolerance thresholds derived from its specific process parameters (focus, dose, alignment), allowing precise quality control without unnecessary rework. This is implemented through the wafer evaluation module that compares individual wafer measurements against their specific simulated thresholds.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting specification thresholds based on actual manufacturing parameters (focus, dose, alignment) rather than using fixed worst-case values. The system simulates metrology data using specific process conditions for each wafer and derives customized tolerance levels, thereby optimizing the balance between reliability and rework rate through parameter-driven specification adaptation.
3Stability of the object's composition
If conventional specification methods are used, then manufacturing robustness is improved, but fabrication time extends
Solution Approach 1:
The patent applies preliminary action by pre-simulating metrology data and determining customized specification thresholds for each wafer before actual metrology measurements are performed. The process condition acquisition module and data simulation module prepare wafer-specific tolerance levels in advance, allowing rapid evaluation of actual measurements against pre-established criteria, thereby reducing fabrication time while maintaining robustness.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting specification thresholds based on actual manufacturing parameters (focus, dose, alignment) rather than using fixed worst-case values. The system simulates metrology data using specific process conditions for each wafer and derives customized tolerance levels, thereby optimizing the balance between reliability and rework rate through parameter-driven specification adaptation.
Data Source
AI summary
Aspects of the disclosed technology relate to techniques for using hotspot simulation to make wafer rework decisions. Metrology data of photoresist patterns created based on a layout design for a circuit design by a photolithographic processing step are received during a lithographic process. Hotspots of interest are selected based on comparing the metrology data with simulated metrology data associated with hotspots. The simulated metrology data and information of the hotspots are generated by performing lithographic simulation on the layout design before the lithographic process and stored in a library of potential hotspots. Lithography simulation is performed on the selected hotspots of interest using process conditions of the photolithographic processing step to generate simulated hotspot data. The simulated hotspot data are analyzed to determine whether rework of the one or more wafers or a wafer lot to which the one or more wafers belong is needed.