Wafer Scale Active Thermal Interposer With Isolation Structures
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Solution Overview
Problem
Conventional methods for testing integrated circuits at the wafer level face challenges in precise heating and cooling, limiting the ability to perform environmental testing effectively, especially in controlling individual die temperatures within a wafer.
Innovation Solution
A wafer scale active thermal interposer device with thermal isolation structures, comprising multiple thermal zones and thermal resistance structures, allows for independent temperature control of different regions of a wafer, enabling precise heating and cooling of individual dice during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional environmental chambers are used for wafer-level testing, then comprehensive environmental testing can be performed, but testing rate is limited due to substantial air volumes and mass of mounting structures
Solution Approach 1:
The patent divides the wafer into multiple independently controllable thermal zones, each corresponding to individual dice or groups of dice. This segmentation allows parallel thermal control of multiple test regions simultaneously, dramatically increasing testing throughput without requiring a single large complex chamber for the entire wafer.
Solution Approach 2:
The patent introduces a thermal interposer as an intermediary layer between the wafer and the testing system. This interposer contains embedded thermal zones and thermal resistance structures that mediate heat distribution, enabling precise independent temperature control of different wafer regions while simplifying the overall testing architecture.
2Measurement precision
If thermal zones are used to control individual die temperatures, then precise temperature control is achieved, but thermal energy conductance between zones causes temperature interference
Solution Approach 1:
The patent extracts or removes thermal pathways between adjacent thermal zones by incorporating thermal resistance structures (such as trenches or insulation layers) at the boundaries between zones. This extraction of thermal conductance prevents heat leakage from one thermal zone to another, ensuring that temperature control in one zone does not interfere with adjacent zones.
Solution Approach 2:
The patent applies different thermal properties to different regions of the interposer. Thermal resistance structures are strategically placed at specific locations between thermal zones to create localized thermal isolation, while maintaining high thermal conductivity within each individual thermal zone for effective temperature control.
3Productivity
If wafer-level testing is performed, then manufacturing throughput is increased, but precise heating and cooling of individual dice is not available
Solution Approach 1:
The patent segments the thermal control system into multiple independent thermal zones that correspond to individual dice or groups of dice on the wafer. Each thermal zone can be independently controlled, allowing precise temperature management for each die while maintaining wafer-level testing capability, thus achieving both high throughput and individual die precision.
Solution Approach 2:
The patent implements dynamically controllable thermal zones with independent temperature regulation capabilities. The thermal zones can be actively adjusted during testing to provide precise heating or cooling as needed for each individual die, enabling adaptive temperature control that maintains manufacturing precision while preserving wafer-level testing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances testing flexibility and accuracy by allowing different areas of a wafer to be controlled at various temperatures, improving manufacturing throughput and identifying defective dice without the need for additional manufacturing steps.
Implementation Method 1
A plurality of thermal resistance structures located between the plurality of thermal zones. The plurality of thermal resistance structures is configured to limit conductance of thermal energy between the plurality of thermal zones.
Implementation Method 2
A first thermal zone of the plurality of thermal zones is configured to apply thermal energy to a first thermal region of the wafer DUT, and a second thermal zone of the plurality of thermal zones is configured to apply thermal energy to a second thermal region of the wafer DUT.
Data Source
AI summary
A system for testing circuits of an integrated circuit semiconductor wafer includes a tester system testing the circuits of the wafer and a test stack coupled to the tester system. The test stack includes a wafer probe for contacting a first surface of the wafer and for probing individual circuits of the circuits of the wafer, a wafer scale active thermal interposer layer operable to contact a second surface of the wafer and containing a plurality of thermal zones corresponding to a die layout of the wafer and further operable to selectively heat areas of the wafer. The thermal zones are thermally isolated using a plurality of thermal resistance structures disposed between the thermal zones.