Wafer-Scale Reconfigurable Logic Fabric for Defect-Tolerant Chiplets
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Solution Overview
Problem
Current wafer-scale integration technologies face challenges such as incompatibility of chiplets, difficulty in dealing with failed components or interconnects, and latency issues in processor-memory communication, which hinder the realization of high-density, reliable, and efficient computational workloads.
Innovation Solution
A novel active and passive wafer-scale fabric that integrates hundreds of closely-spaced bare-die chips, such as memory, GPUs, FPGAs, and AI accelerators, into a single wafer, enabling higher bandwidth and lower connectivity loss through reconfigurable logic fabrics and micro-bump integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional PCB integration techniques are used, then ease of manufacture is maintained, but compute density and system volume are severely limited
Solution Approach 1:
The system is divided into multiple chiplets that are integrated onto a wafer-scale substrate. Each chiplet can be independently manufactured and tested, then assembled into the final wafer-scale system. This segmentation enables high compute density while maintaining manufacturing feasibility through modular assembly processes.
Solution Approach 2:
The patent transitions from traditional 2D PCB integration to 3D wafer-scale integration, stacking multiple chiplet layers vertically on a single wafer substrate. This dimensional change dramatically increases compute density by utilizing vertical space, achieving up to 10x higher integration density compared to conventional PCB approaches.
2Volume of moving object
If wafer-scale integration is implemented, then system volume is reduced, but manufacturing precision and quality control become more challenging
Solution Approach 1:
Chiplets are pre-manufactured, tested, and characterized individually before integration onto the wafer substrate. This preliminary action ensures that only qualified chiplets are assembled, simplifying quality control at the wafer scale. Defects can be identified and isolated at the chiplet level rather than requiring complete wafer rework.
Solution Approach 2:
The patent employs advanced packaging parameters including micro-bump technologies with sub-50 micrometer pitch, controlled thermal profiles during assembly, and precision alignment mechanisms. These parameter changes enable high-density integration while maintaining manufacturing precision through optimized process conditions.
3Adaptability or versatility
If heterogeneous chiplets are integrated, then adaptability and functionality are enhanced, but interconnect compatibility and integration difficulty increase
Solution Approach 1:
The wafer substrate provides a universal interconnect architecture that can accommodate multiple chiplet types with different functionalities (CPU, GPU, memory, I/O). Standardized interface protocols and physical connection methods enable heterogeneous chiplets to be integrated using the same manufacturing process, achieving both functional diversity and manufacturing simplicity.
Solution Approach 2:
The wafer substrate acts as an intermediary platform that mediates between heterogeneous chiplets with different interconnect requirements. It provides protocol conversion, signal conditioning, and physical interfacing that enables incompatible chiplet types to communicate seamlessly, simplifying the integration of diverse functional components.
4Quantity of substance
If chiplets are placed closer together, then IO density and thermal characteristics improve, but reliability and defect tolerance decrease
Solution Approach 1:
The wafer-scale integration incorporates redundant interconnect paths and error correction mechanisms built into the substrate architecture before assembly. This beforehand cushioning provides defect tolerance by offering alternative signal routes and correction capabilities that compensate for potential failures in closely-spaced chiplet interconnects.
Solution Approach 2:
The system employs dynamic reconfiguration capabilities that can adapt interconnect paths in real-time based on detected defects or performance requirements. This dynamic routing allows the system to maintain reliability by dynamically avoiding faulty pathways while utilizing the high-density interconnect architecture for optimal performance.
Data Source
AI summary
A novel active and passive wafer-scale fabric is disclosed that allows for the integration of very-large-scale integrated circuits (ICs) with hundreds of closely-spaced bare-die chips such as memory, GPUs, FPGAs and AI accelerators into a single wafer. The wafer-scale logic fabric allows the tiling of known good chips to make systems that perform as a single-chip monolithic device, despite comprising several smaller heterogeneous chips. This approach enables higher bandwidth and lower connectivity loss than conventional circuit board packaging, which is especially critical for AI computing and signal/image processing applications. Further, it also allows for multiple levels of high-density connections, since this architecture allows wiring between chips to be as small as the wiring within a chip. This wafer-scale platform combined with heterogeneous IP block/chiplets and μ-bump integration produces a chip-like wiring for the wafer-scale heterogeneous multi-chip system where part of chip can be removed or reconfigured.