Wafer-Scale Semiconductor Assembly With Integrated Cooling and Power Delivery
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high performance computing and thermal management for AI applications due to limitations in wafer-scale integration, power integrity, and thermal mechanical stress, particularly in advanced silicon nodes and organic substrates.
Innovation Solution
The integration of CPUs, GPUs, and ASICs in a wafer-scale or panel-scale Si or glass substrate with redistribution layers, voltage regulator modules, integrated stacked capacitors, liquid cooling channels, and thermal vias to enhance power integrity and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If wafer-scale integration is used to increase chip count and performance, then computing performance improves, but thermal management becomes more difficult
Solution Approach 1:
The patent segments the wafer-scale substrate into multiple independent cooling zones, each with dedicated thermal management resources. This allows localized temperature control for different chip regions, enabling high-performance computing while managing heat dissipation effectively across the large substrate area.
Solution Approach 2:
The patent introduces an intermediary thermal management layer between the chips and the cooling system. This layer includes thermal interface materials, heat spreaders, and temperature sensors that mediate heat transfer, allowing efficient thermal management while maintaining high computing performance across the wafer-scale integration.
2Power
If more chips are integrated in a larger package footprint, then computing performance improves, but power integrity becomes more challenging
Solution Approach 1:
The patent transitions from two-dimensional power distribution to three-dimensional power delivery networks. Multiple power delivery layers are stacked vertically within the wafer-scale substrate, with through-silicon vias and embedded capacitors providing power integrity across all chips regardless of their distance from the package edges, enabling high-performance computing with reliable power distribution.
3Productivity
If wafer-scale device is used to increase integration density, then productivity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary actions during the wafer fabrication process, including pre-configured redistribution layers, pre-formed through-silicon vias, and pre-integrated passive components. This preliminary preparation enables high integration density while reducing the precision requirements for subsequent assembly steps, as the wafer-scale substrate arrives at the assembly stage with much of the complex interconnect structure already in place.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves power distribution network performance, thermal dissipation, and mechanical support, enabling larger chip integration and higher yield in semiconductor devices, addressing the limitations of traditional wafer-level packaging techniques.
Implementation Method 1
liquid cooling channels may be created within the Si or glass substrate to help manage the thermal dissipation of the semiconductor device. Thermal vias may also be provided within the Si or glass substrate for better thermal management.
Implementation Method 2
A liquid cooling cold plate may be attached to the backside of the Si or glass substrate for better thermal management.
Data Source
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AI summary
Semiconductor devices and methods of manufacturing the semiconductor devices are provided. For example, a semiconductor device may include: a substrate; and semiconductor assemblies that are configured to be electrically connected together, each of the semiconductor assemblies including: a first semiconductor chip that is at least partially between a first surface of the substrate and a second surface of the substrate, the first surface facing in a first direction and the second surface facing in a second direction, opposite to the first direction; and a voltage regulator that is on the first surface of the substrate, overlaps with the first semiconductor chip in the first direction, and is configured to be electrically connected to the first semiconductor chip.