Wafer-Scale IC Encapsulation via Pre-Dicing Polymer Coating

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Solution Overview

Problem

Conventional semiconductor packaging methods require post-fabrication processing of individual die to cover the edges, which is costly and inefficient, as the polymer or assembly layer does not cover the sides of the die after they are cut from the wafer.

Innovation Solution

The waferscale packaging method uses a wafer transfer technology where a polymer is applied to both sides and top of the die before singulation, ensuring complete encapsulation of the die while still in wafer form, using a carrier wafer and dicing through polymer layers to maintain protection and facilitate handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional dicing is performed to cut die from the wafer, then individual die can be separated for assembly, but the edges of the die are not covered by polymer or assembly material requiring additional post-processing

Engineering Contradiction:
Improveease of manufactureVSAvoidedge protection
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies polymer material to the wafer surface before the dicing step, so that when the die are cut from the wafer, the polymer already covers the edges of each die. This preliminary application of packaging material eliminates the need for subsequent edge coverage operations on individual die, resolving the contradiction between ease of manufacture and edge protection by performing the protective action before the cutting action that would expose edges

Inventive Principle:
Principle #10Preliminary action

2Reliability

If polymer is applied after dicing to cover die edges, then edge protection is achieved, but additional post-fabrication processing steps are required increasing cost and complexity

Engineering Contradiction:
Improveedge protectionVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The polymer application is performed before dicing rather than after, consolidating the packaging process into fewer steps. The polymer is applied to the intact wafer surface, then the wafer is diced through the polymer layer, automatically providing edge coverage without requiring separate post-dicing application steps, thus reducing process complexity while maintaining edge protection

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If individual die are processed separately after dicing, then each die can be assembled, but handling and assembly costs increase

Engineering Contradiction:
Improveease of operationVSAvoidproduction efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent keeps multiple die connected through the polymer material after dicing, allowing them to be handled and assembled as a group or array rather than as individual separate components. This merging of multiple die into a single handleable unit reduces the number of handling operations required and improves production efficiency while maintaining ease of operation through the unified structure

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9209047B1Method of producing encapsulated IC devices on a wafer
Publication Date: 2015.12.08 AMERICAN SEMICON
  • US9209047B1 patent drawing
  • US9209047B1 patent drawing
  • US9209047B1 patent drawing

AI summary

This method of waferscale packaging produces finished integrated circuits (ICs) individually completely encapsulated with environmentally protective packaging material while still in the wafer format. Following conventional semiconductor fabrication of chips at the wafer level and prior to their separation, a first polymer is applied to the front surface of the wafer with allowance for contact holes. A carrier wafer is attached to the exposed polymer. The original substrate is removed and the devices are separated by cutting through the semiconductor layer and the first polymer. A second polymer is applied to cover the exposed backside of the devices and to fill the cut spaces between them, thereby sealing the remaining five surfaces of the chips. The second polymer layer may also include contact holes for access to the back side of the device chips. A second singulation cutting leaves the chips on the wafer prepared for a pick-and-place operation.