Wafer-Scale Interposer Packaging for High-Density Die Integration
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Solution Overview
Problem
The increasing density of input/output (I/O) pads on integrated circuit dies due to their miniaturization and functional integration poses challenges in die packaging, particularly in terms of interconnect density and flexibility, as the area available for I/O pads decreases, making conventional packaging technologies less effective.
Innovation Solution
The use of wafer scale interposers without silicon, combined with redistribution layers, allows for high interconnect density and flexible routing by enabling multiple dies to be integrated on a single wafer, overcoming reticle size limitations through stitching technology and supporting electrical interconnects between dies, and allowing for single or double-sided assembly to enhance yield and design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional packaging technologies are used with miniaturized dies, then die size is reduced and functional integration is increased, but I/O pad density increases and packaging difficulty increases
Solution Approach 1:
The patent introduces an interposer as an intermediary component between the integrated circuit die and the substrate. This interposer includes a redistribution layer with conductive structures that redistribute I/O pads from the die to different locations on the substrate, effectively mediating the connection and resolving the packaging difficulty caused by high I/O pad density
Solution Approach 2:
The patent utilizes three-dimensional stacking architecture where multiple dies are stacked vertically on the substrate rather than being placed side-by-side. This vertical arrangement in the third dimension allows for higher functional integration while maintaining manageable I/O pad density on each individual die and simplifying the packaging process
2Productivity
If I/O pad density is increased to accommodate more functions, then functional integration is improved, but the area available for each I/O pad decreases
Solution Approach 1:
The patent employs 3D stacking to distribute I/O pads across multiple vertical layers, effectively utilizing the third dimension to increase the total I/O capacity without reducing the area available for each individual pad on any single die layer
3Quantity of substance
If multiple dies are integrated on a single wafer, then interconnect density is improved, but reticle size limitations are encountered
Solution Approach 1:
The patent divides the wafer into multiple segments or tiers, with each tier containing a manageable number of dies that can be processed with standard reticle sizes. The segmentation allows for high overall interconnect density while avoiding the need for oversized reticles that would be required to pattern all dies on a single large wafer
Data Source
AI summary
A semiconductor device includes a first plurality of dies on a wafer, a first redistribution structure over the first plurality of dies, and a second plurality of dies on the first redistribution structure opposite the first plurality of dies. The first redistribution structure includes a first plurality of conductive features. Each die of the first plurality of dies are bonded to respective conductive features of the first plurality of conductive features by metal-metal bonds on a bottom side of the first redistribution structure. Each die of the second plurality of dies are bonded to respective conductive features of the first plurality of conductive features in the first redistribution structure by metal-metal bonds on a top side of the first redistribution structure.