Wafer-Scale Semiconductor Packaging for High-Density I/O Routing
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Solution Overview
Problem
The increasing density of input/output (I/O) pads on integrated circuit dies due to their miniaturization poses challenges in packaging, as the area available for these pads decreases, making it difficult to achieve high interconnect density and flexible routing in conventional packaging technologies.
Innovation Solution
The use of non-silicon interposers and redistribution layers in fan-out packages allows for high interconnect density and flexible routing by forming wafer-scale multi-chip packages, where multiple dies are integrated on a wafer-scale interposer with back-end-of-line layers, enabling electrical interconnects between dies and overcoming reticle size limitations through stitching technology or wafer-scale masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integrated circuit dies are miniaturized to increase functionality, then the number of I/O pads needed increases, but the area available for I/O pads decreases
Solution Approach 1:
The patent employs fan-out packaging technology that redistributes I/O pads from the original die surface to a larger area on the package substrate. This dimensional expansion allows the same number of I/O pads to be accommodated on a larger effective area, resolving the contradiction between increasing I/O pad quantity and limited die area.
Solution Approach 2:
The patent introduces an intermediary packaging structure (fan-out package) that acts as a mediator between the miniaturized die and the external connection environment. This intermediary redistributes the I/O pads to a larger area on the package substrate, enabling high I/O density without increasing the die area.
2Quantity of substance
If I/O pad density is increased on miniaturized dies, then more functions can be integrated, but the difficulty of die packaging increases
Solution Approach 1:
The fan-out packaging technology redistributes high-density I/O pads from the compact die surface to a larger area on the package substrate, effectively moving the density challenge from the die level to the package level where it can be more easily managed.
Solution Approach 2:
The patent separates the die from the final package structure, allowing the I/O pad redistribution to occur on the package substrate rather than on the die itself. This segmentation enables independent optimization of die design and package layout, reducing packaging difficulty.
3Ease of manufacture
If conventional packaging technologies are used for high-density I/O pads, then manufacturing is simpler, but interconnect density and routing flexibility are limited
Solution Approach 1:
The fan-out package acts as an intermediary structure that provides routing flexibility between the die and external connections. The package substrate serves as a flexible interconnection layer that can route signals to various locations, enabling adaptable routing while maintaining manufacturing feasibility.
Solution Approach 2:
By moving I/O pad redistribution to the package substrate level, the system gains additional spatial dimensions for routing flexibility. The package substrate allows signals to be routed to locations that would be impossible to reach from the compact die surface, enhancing adaptability without complicating die manufacturing.
Data Source
AI summary
A semiconductor device includes a first plurality of dies on a wafer, a first redistribution structure over the first plurality of dies, and a second plurality of dies on the first redistribution structure opposite the first plurality of dies. The first redistribution structure includes a first plurality of conductive features. Each die of the first plurality of dies are bonded to respective conductive features of the first plurality of conductive features by metal-metal bonds on a bottom side of the first redistribution structure. Each die of the second plurality of dies are bonded to respective conductive features of the first plurality of conductive features in the first redistribution structure by metal-metal bonds on a top side of the first redistribution structure.


