Wafer-Scale Satellite Bus Stacking Functional Diced Circuits
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Solution Overview
Problem
Traditional satellite manufacturing methods result in heavy, costly spacecraft with high failure risks and limited modularity, making them unsuitable for low-drag missions and large constellations.
Innovation Solution
The development of a wafer-scale satellite bus using wafer reconstruction techniques to stack functional diced circuits, allowing for various subsystem functions like propulsion, attitude control, and communication, with modular design enabling easy replacement and reordering of wafers, and surface-mounting of mission-specific components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If traditional satellite manufacturing methods are used, then structural integrity and subsystem integration are achieved, but weight and fabrication cost increase significantly
Solution Approach 1:
The satellite is divided into multiple functional wafers that can be manufactured independently using standard semiconductor fabrication processes. Each wafer contains specific subsystems (propulsion, attitude control, power, etc.), allowing parallel manufacturing and reducing overall fabrication complexity while minimizing weight through precise material placement.
Solution Approach 2:
The patent transitions from traditional three-dimensional mechanical assembly to a two-dimensional wafer stacking architecture. Functional circuits are fabricated on planar wafers and then stacked vertically, enabling complex satellite systems to be built using flat, manufacturable components that can be produced at scale with reduced weight.
2Adaptability or versatility
If traditional satellite buses are used, then subsystem integration is achieved, but modularity and adaptability are limited
Solution Approach 1:
The satellite bus is segmented into standardized wafers with uniform interfaces, allowing different mission-specific payloads to be integrated by simply stacking different functional wafers in different configurations. This maintains high adaptability while reducing integration complexity through standardization.
Solution Approach 2:
The patent creates a universal wafer platform that can support multiple mission types by changing the stack configuration. The same basic wafer architecture can be adapted for communications, Earth observation, navigation, or scientific missions, providing versatility without requiring complex custom integration for each mission.
3Productivity
If traditional manufacturing scales are used, then production capability is sufficient, but cost and weight reduction potential are lost
Solution Approach 1:
The satellite manufacturing process is segmented into wafer fabrication and wafer stacking phases, allowing high-volume production of identical wafers using automated semiconductor manufacturing. This dramatically improves productivity while keeping individual satellite weight minimal, as only essential functional materials are used in precise quantities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves significant weight and cost reductions, enabling low-drag missions and large constellations with reduced failure risks, while allowing for flexible mission-specific designs and efficient production.
Implementation Method 1
bonding the processed wafers to form the satellite in a stack
Data Source
AI summary
A wafer-scale satellite bus and a manner of making the same include using wafer reconstruction techniques to stack functional diced circuits onto each other and bond them. The disclosed techniques allow for a variety of functions in each die, including providing, without limitation: ground-based communications, attitude and propulsion control, fuel tanks and thrusters, and power generation. The wafers are initially manufactured according to a common wafer design that provides electrical and power interconnects, then different wafers are further processed using subsystem-specific techniques. The circuits on differently-processed wafers are reconstructed into a single stack using e.g. wafer bonding. Surface components are mounted, and the circuitry is diced to form the final satellites. Mission-specific functions can be incorporated, illustratively by surface-mounting, to the bus at an appropriate stage of assembly, on-wafer circuitry or instrument packages for performing these functions.