Wafer Scribe Trench Dielectric Layout for Low-Debris Dicing
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Solution Overview
Problem
Current methods for producing display devices for augmented reality (AR) and virtual reality (VR) applications face challenges due to the use of long wires or metal interconnections, which consume space and complicate mounting, necessitating an improvement in the semiconductor device fabrication process.
Innovation Solution
A method involving defining a scribe line on a wafer with an inter-metal dielectric (IMD) layer and an alternating stack, removing part of the stack to form a trench, filling it with a dielectric layer of higher dielectric constant, and then dicing the wafer to create chips with an aligned dielectric layer on the sidewalls, enhancing the fabrication process for AR and VR devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If long wires or metal interconnections are used to connect DDICs to display module, then electrical connection is achieved, but space consumption increases and mounting difficulty increases
Solution Approach 1:
The patent transitions from planar wire connections to three-dimensional vertical stacking by forming alternating stacks of conductive and dielectric layers. This allows electrical connections to be established in the vertical dimension rather than requiring long horizontal wire runs, thereby reducing space consumption while maintaining electrical connectivity.
Solution Approach 2:
The patent implements nested structures by forming conductive layers and dielectric layers in alternating stacks, where conductive patterns are embedded within dielectric layers. This nested arrangement allows multiple connection levels to be compactly organized vertically, reducing the overall space required for interconnections.
2Reliability
If long wires or metal interconnections are used to connect DDICs to display module, then electrical connection is achieved, but mounting difficulty increases
Solution Approach 1:
By moving from two-dimensional wire routing to three-dimensional vertical stacking, the patent simplifies the mounting process. The alternating stacks provide structured, pre-organized connection points that are easier to align and connect compared to managing long flexible wires, thereby improving ease of operation.
Solution Approach 2:
The patent segments the interconnection structure into discrete alternating layers of conductive and dielectric materials. This segmentation creates modular connection units that can be independently positioned and connected, simplifying the mounting process compared to handling continuous long wires.
3Ease of manufacture
If dicing is performed directly without filling scribe line with high dielectric constant material, then fabrication process is simpler, but debris is generated during dicing
Solution Approach 1:
The patent applies preliminary action by filling the scribe line with dielectric material having a higher dielectric constant than the surrounding dielectric layers before performing the dicing process. This preparatory step creates a distinct mechanical and electrical boundary that reduces debris generation during subsequent dicing operations, while adding only one additional fabrication step.
Data Source
AI summary
A method for fabricating a semiconductor device includes the steps of first defining a scribe line on a front side of a wafer, in which the wafer includes an inter-metal dielectric (IMD) layer disposed on a substrate and an alternating stack disposed on the IMD layer. Next, part of the alternating stack is removed to form a trench on the front side of the wafer, a dielectric layer is formed in the trench, and then a dicing process is performed along the scribe line from a back side of the wafer to divide the wafer into chips.