Semiconductor Wafer Scribe Line Dummy Patterns for Stress Balancing
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Solution Overview
Problem
Conventional scribe line structures in semiconductor wafers are prone to mechanical stress, cracking, and peeling during die separation, compromising the integrity and reliability of integrated circuit devices, especially with the use of diamond saws and laser scribing, which also results in defects and reduced image sensor quality due to brittle low-k dielectric materials and weak bonding interfaces.
Innovation Solution
Incorporating dummy patterns or structures in the scribe lines and die areas, such as polygonal shapes, to balance mechanical and residual stresses during die separation, using techniques like etching and die sawing, which can reduce delamination and improve the integrity and reliability of IC devices and image sensor uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If diamond saw is used for dicing, then throughput is improved, but mechanical stress causes cracking at die edges
Solution Approach 1:
The patent applies preliminary action by forming stress compensation structures (dummy patterns) in the scribe lines before the dicing process. These structures are created during fabrication to preemptively counteract the mechanical stress that will be introduced during diamond saw cutting, thereby preventing cracking while maintaining high throughput
2Reliability
If laser scribing is used as alternative to diamond saw, then cracking is reduced, but throughput decreases and cost increases
Solution Approach 1:
The patent introduces stress compensation structures as an intermediary element in the scribe lines that mediate between the diamond saw cutting process and the die structure. These structures absorb and distribute mechanical stress, enabling the use of fast diamond saw dicing without the cracking problems that would otherwise require slower laser scribing
3Manufacturing precision
If low-k or ELK dielectric materials are used, then cross coupling and parasitic capacitance are reduced, but peeling and cracking increase during dicing
Solution Approach 1:
The patent applies local quality by placing stress compensation structures specifically in the scribe line areas where cutting stress concentrates, while maintaining the low-k or ELK dielectric materials in the active die areas for signal integrity. This localized approach allows each region to have the properties needed for its specific function
4Ease of operation
If scribing is performed on test pads in scribe line areas, then wafer-level testing is enabled, but severe dielectric peeling and cracking occur
Solution Approach 1:
The patent uses preliminary action by pre-forming stress compensation structures in the scribe lines before any cutting or testing operations. These structures are in place beforehand to prevent the severe peeling and cracking that would otherwise occur during scribing of test pads, enabling reliable wafer-level testing
Data Source
AI summary
A semiconductor wafer having a plurality of chip die areas arranged on a wafer in an array, each chip die area including a seal ring area with one or more first sets of polygonal structures. The wafer further comprises scribe line areas between the chip die areas, the scribe line areas including one or more second sets of polygonal structures. The presence of proximate polygonal structures between the scribe line and seal ring areas balance stresses between the chip die areas during wafer dicing operation.