Wafer Scribe Lane External Pads for Parallel Die Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for testing integrated circuits on wafers are time-consuming due to the need to physically move the wafer between dies, which wastes time and can damage internal pads, and require complex and resource-intensive automated test equipment, while also limiting high-frequency testing capabilities.
Innovation Solution
A wafer design with external pads and integrated components in the scribe lanes, allowing for electronic selection and testing of dies without mechanical movement, using conductive tracks and external test components to reduce the need for internal pad contact and simplify the testing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the wafer is mechanically moved relative to the probe card for each die testing, then each die can be tested sequentially, but the testing time increases significantly due to the mechanical movement time
Solution Approach 1:
The invention segments the testing function by creating multiple independent test circuits on the wafer itself, allowing different dies to be tested through different segments (test circuits) simultaneously. This eliminates the need to mechanically move the wafer for each die, as each die can be accessed through its dedicated test circuit in parallel.
Solution Approach 2:
The invention transitions from a one-dimensional sequential testing approach (testing one die at a time by moving the wafer) to a two-dimensional parallel testing approach by incorporating multiple test circuits across the wafer surface. This allows simultaneous testing of multiple dies through different spatial locations, effectively utilizing the wafer's surface area for parallel operations.
2Productivity
If several dies are tested in parallel, then the testing time is reduced, but the automated test equipment and probe card complexity increase
Solution Approach 1:
The invention extracts the test circuit functionality from the external probe card and relocates it onto the wafer itself. By integrating test circuits directly on the wafer, the probe card's complexity is reduced as it no longer needs to contain all the test circuitry, while still enabling parallel testing of multiple dies through the wafer's embedded test circuits.
Solution Approach 2:
The invention introduces an intermediary layer of test circuits on the wafer that mediates between the simple probe card and the dies being tested. These intermediary test circuits handle the complex testing functions locally on the wafer, allowing the probe card to remain relatively simple while still achieving parallel testing capabilities.
3Reliability
If larger pads are used for wafer testing, then the testing connections are more robust, but the die size increases
Solution Approach 1:
The invention creates copies of the test interface by providing multiple test circuits across the wafer, each with its own set of pads. This allows the use of smaller individual pads for each test circuit while maintaining overall testing capability through parallel access. The functional redundancy of multiple test circuits compensates for the reduced size of individual pads.
Data Source
AI summary
A wafer comprises i) at least one independent die having internal integrated components, a multiplicity of internal pads connected to some of the internal integrated components, ii) scribe lanes defined between and around each independent die, and in part of which are defined, for each die, at least a first group of external pads and/or a second group of external test integrated components. The external pads of each first group are connected, through conductive tracks, to a chosen one of the internal pads and/or internal integrated components of the associated die, and arranged to be fed with chosen test signals or to collect test result signals. Each external test integrated components of each second group is connected, through conductive tracks, to a chosen one of the die internal pads and/or die internal integrated components and/or to external pads of a first group.