Semiconductor Wafer Scribe Line Layout for Narrower Plasma Dicing
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Solution Overview
Problem
The increasing demand for smaller, high-speed semiconductor devices has led to challenges in maintaining yield and throughput during the dicing process of semiconductor wafers, as the number of chips per wafer increases, making the separation of chips more complex and time-consuming.
Innovation Solution
A semiconductor wafer design featuring a separation zone with a scribe line configured for plasma etching, utilizing plasma etch-resistant material layers and a passivation layer to define the inlet area, which reduces the width of the separation zone and enhances the dicing process efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of chips per wafer is increased to meet demand, then productivity is improved, but the dicing time and process complexity increase
Solution Approach 1:
The separation zone is divided into multiple distinct layers: plasma etch-resistant material layers extending from chip peripheral walls, a passivation layer hermetically sealing the inlet area, and the scribe line material stack. This segmentation allows each layer to perform its specific function efficiently, enabling faster plasma etching while maintaining chip integrity
Solution Approach 2:
The plasma etch-resistant material layers and passivation layer are pre-configured in the separation zone before the dicing process. The inlet area is pre-defined by the overlapping free ends of the plasma etch-resistant material layers, so that when plasma etching is applied, the process can immediately proceed without additional preparation steps
2Productivity
If the number of chips per wafer is increased to meet demand, then productivity is improved, but device complexity increases
Solution Approach 1:
The separation zone structure is specifically designed with localized features: plasma etch-resistant material layers positioned at the inlet area extending from chip peripheral walls, and a passivation layer selectively sealing only the inlet area. This local quality differentiation simplifies the overall dicing process by providing clear structural cues for the etching process
Solution Approach 2:
The separation zone employs a composite structure combining plasma etch-resistant material layers (resistant to plasma etching) with a passivation layer (hermetically sealing). This composite material approach creates a well-defined inlet area that guides the plasma etching process, reducing complexity by providing clear boundaries between chips
3Productivity
If the separation zone width is reduced to increase chips per wafer, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The plasma etch-resistant material layers extend vertically from the chip peripheral walls into the separation zone, creating a three-dimensional structure that defines the inlet area. This vertical extension provides precise lateral boundaries for the separation zone, enabling reduced width while maintaining manufacturing precision through the overlapping configuration of these extended layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution optimizes the dicing process by reducing the width of the separation zone and improving the separation efficiency, especially for chips with small dimensions, thereby increasing the number of chips per wafer and reducing production costs.
Implementation Method 1
a scribe line configured to be diced using plasma etching
Data Source
AI summary
A semiconductor wafer (1a, 1b) including a plurality of chips (2) and a separation zone (3) spacing the semiconductor chips (2) from each other in this wafer (1a, 1b), such a separation zone (3) extending from a front face (4a) to an opposite backside face (4b) of this wafer (1a, 1b), this separation zone (3) includes a scribe line (6) configured to be diced using plasma etching and an inlet area (13) of this scribe line (6), the inlet (13) being delimitated by free ends of plasma etch-resistant material layers (9) extending each from a peripheral wall (20) of a functional part (18) of a chip (2) into the scribe line (6) by overlapping a top of a seal ring (7) of this chip (2).