Wafer Scribe Line Notch Layout for Clean Die Separation

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Solution Overview

Problem

As semiconductor device integration increases, the narrow scribe lines between dies make blade sawing difficult, and metal materials on the scribe lines obstruct the dicing process, requiring an improved method to enhance wafer divisibility and facilitate stress concentration during dicing.

Innovation Solution

The introduction of notch patterns in open areas within the scribe lines, where the metal material layer is locally removed, to concentrate crack stress and guide the division energy vertically, thereby improving wafer divisibility and preventing obstacles during the dicing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the scribe line width is decreased to increase integration density, then the number of dies per wafer increases, but blade sawing becomes difficult and wafer divisibility deteriorates

Engineering Contradiction:
Improvenumber of dies per waferVSAvoidwafer divisibility
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

Notch patterns are formed in the scribe line regions before the dicing process to pre-concentrate stress at specific locations. This preliminary action enables crack propagation to occur predictably along the scribe lines even when they are narrow, thus maintaining wafer divisibility while allowing increased integration density

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The metal material layer is selectively removed only in the scribe line regions to create open areas with notch patterns, while the metal layer remains intact in the die regions. This local modification concentrates stress at the notch locations during dicing, enabling clean separation without affecting the overall wafer structure or die integrity

Inventive Principle:
Principle #3Local quality

2Reliability

If the metal material layer is present on the scribe line, then electrical connectivity is maintained, but it obstructs the dicing process and prevents effective stress concentration

Engineering Contradiction:
Improveelectrical connectivityVSAvoiddicing process
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The metal material layer is extracted (removed) specifically from the scribe line regions to create open areas where notch patterns can be formed. This extraction eliminates the obstruction to stress concentration and dicing while the metal layer remains preserved in the die regions to maintain electrical connectivity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The metal material layer is segmented into two regions: removed from scribe line areas to enable dicing, and retained in die areas to maintain electrical connectivity. This segmentation allows the system to simultaneously achieve both dicing facilitation and electrical connectivity

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances wafer divisibility by concentrating crack stress and ensuring efficient dicing without debris, allowing for narrower kerfs and preventing issues like film delamination and metal line contact problems.

Implementation Method 1

one or more notch patterns each indicating a direction in which the scribe line region extends are disposed in each of the open areas to concentrate crack stress, thereby increasing divisibility of a wafer

Methodology Applied
Scientific EffectStress concentration: Fracture Mechanics

Data Source

PatentUS11804446B2Semiconductor device
Publication Date: 2023.10.31 SK HYNIX INC
  • US11804446B2 patent drawing
  • US11804446B2 patent drawing
  • US11804446B2 patent drawing

AI summary

Provided is a semiconductor device capable of improving the divisibility of a wafer by concentrating crack stress by disposing notch patterns on a scribe line of a wafer, by locally removing a metal thin film in a scribe line and propagating a dividing energy in a vertical direction of a die surface. A semiconductor device includes: die regions spaced apart from each other in a wafer, scribe line regions disposed between neighboring ones of the die regions and covered with a metal material layer, and one or more open areas disposed in each of the scribe line regions and formed by locally removing the metal material layer, wherein each of the open areas includes one or more notch patterns indicating a direction in which the scribe line region is extended.